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Randy Huang
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2020 – today
- 2024
- [j4]Peter M. VanNostrand, Dennis M. Hofmann, Lei Ma, Belisha Genin, Randy Huang, Elke A. Rundensteiner:
Counterfactual Explanation Analytics: Empowering Lay Users to Take Action Against Consequential Automated Decisions. Proc. VLDB Endow. 17(12): 4349-4352 (2024) - [c10]Xinwei Fu, Zhen Zhang, Haozheng Fan, Guangtai Huang, Mohammad El-Shabani, Randy Huang, Rahul Solanki, Fei Wu, Ron Diamant, Yida Wang:
Distributed Training of Large Language Models on AWS Trainium. SoCC 2024: 961-976 - 2023
- [i2]Milan Ganai, Haichen Li, Theodore Enns, Yida Wang, Randy Huang:
Target-independent XLA optimization using Reinforcement Learning. CoRR abs/2308.14364 (2023) - 2022
- [j3]Tianlong Chen, Zhenyu Zhang, Jun Wu, Randy Huang, Sijia Liu, Shiyu Chang, Zhangyang Wang:
Can You Win Everything with A Lottery Ticket? Trans. Mach. Learn. Res. 2022 (2022) - 2020
- [i1]Hongbin Zheng, Sejong Oh, Huiqing Wang, Preston Briggs, Jiading Gai, Animesh Jain, Yizhi Liu, Rich Heaton, Randy Huang, Yida Wang:
Optimizing Memory-Access Patterns for Deep Learning Accelerators. CoRR abs/2002.12798 (2020)
2010 – 2019
- 2017
- [c9]Philip Colangelo, Randy Huang, Enno Lübbers, Martin Margala, Kevin Nealis:
Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA. FCCM 2017: 135 - [c8]Eriko Nurvitadhi, Ganesh Venkatesh, Jaewoong Sim, Debbie Marr, Randy Huang, Jason Ong Gee Hock, Yeong Tat Liew, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra, Guy Boudoukh:
Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks? FPGA 2017: 5-14 - [c7]Philip Colangelo, Enno Lübbers, Randy Huang, Martin Margala
, Kevin Nealis:
Application of convolutional neural networks on Intel® Xeon® processor with integrated FPGA. HPEC 2017: 1-7 - 2016
- [c6]Herman Schmit, Randy Huang:
Dissecting Xeon + FPGA: Why the integration of CPUs and FPGAs makes a power difference for the datacenter: Invited Paper. ISLPED 2016: 152-153
2000 – 2009
- 2006
- [j2]André DeHon, Randy Huang, John Wawrzynek:
Stochastic spatial routing for reconfigurable networks. Microprocess. Microsystems 30(6): 301-318 (2006) - [j1]André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek:
Stream computations organized for reconfigurable execution. Microprocess. Microsystems 30(6): 334-354 (2006) - 2003
- [c5]Randy Huang, John Wawrzynek, André DeHon:
Stochastic, spatial routing for hypergraphs, trees, and meshes. FPGA 2003: 78-87 - 2002
- [c4]André DeHon, Randy Huang, John Wawrzynek:
Hardware-Assisted Fast Routing. FCCM 2002: 205- - [c3]Yury Markovsky, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon:
Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. FPGA 2002: 196-205 - 2000
- [c2]Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon:
Stream Computations Organized for Reconfigurable Execution (SCORE). FPL 2000: 605-614
1990 – 1999
- 1999
- [c1]William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, George Varghese, John Wawrzynek, André DeHon:
HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array. FPGA 1999: 125-134
Coauthor Index
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