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Yuze Chi
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2020 – today
- 2024
- [j8]Moazin Khatti
, Xingyu Tian
PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs. ACM Trans. Reconfigurable Technol. Syst. 17(3): 42:1-42:31 (2024) - [c25]Neha Prakriya
TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs. ASPLOS (3) 2024: 966-980 - 2023
- [j7]Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong:
Democratizing Domain-Specific Computing. Commun. ACM 66(1): 74-85 (2023) - [j6]Young Kyu Choi
TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2423-2427 (2023) - [j5]Xingyu Tian
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs. ACM Trans. Reconfigurable Technol. Syst. 16(2): 28:1-28:33 (2023) - [j4]Licheng Guo
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 16(4): 59:1-59:30 (2023) - [j3]Licheng Guo
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design. ACM Trans. Reconfigurable Technol. Syst. 16(4): 63:1-63:31 (2023) - [c24]Moazin Khatti, Xingyu Tian, Yuze Chi, Licheng Guo, Jason Cong, Zhenman Fang:
PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs. FCCM 2023: 12-22 - [c23]Linghao Song
Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver. FPGA 2023: 247-258 - [i13]Neha Prakriya, Yuze Chi, Suhail Basalama, Linghao Song, Jason Cong:
TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs. CoRR abs/2311.10189 (2023) - 2022
- [c22]Atefeh Sohrabizadeh, Yuze Chi, Jason Cong:
StreamGCN: Accelerating Graph Convolutional Networks with Streaming Processing. CICC 2022: 1-8 - [c21]Linghao Song
Serpens: a high bandwidth memory based accelerator for general-purpose sparse matrix-vector multiplication. DAC 2022: 211-216 - [c20]Licheng Guo, Pongstorn Maidee
RapidStream: Parallel Physical Implementation of FPGA HLS Designs. FPGA 2022: 1-12 - [c19]Linghao Song
Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication. FPGA 2022: 65-77 - [c18]Atefeh Sohrabizadeh, Yuze Chi, Jason Cong:
SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity Computation. FPGA 2022: 156 - [c17]Yuze Chi, Licheng Guo, Jason Cong:
Accelerating SSSP for Power-Law Graphs. FPGA 2022: 190-200 - [c16]Linghao Song, Yuze Chi, Jason Cong:
PYXIS: An Open-Source Performance Dataset Of Sparse Accelerators. ICASSP 2022: 76-80 - [i12]Xingyu Tian, Zhifan Ye, Alec Lu, Licheng Guo, Yuze Chi, Zhenman Fang:
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs. CoRR abs/2208.10770 (2022) - [i11]Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong:
TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design. CoRR abs/2209.02663 (2022) - [i10]Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong:
Democratizing Domain-Specific Computing. CoRR abs/2209.02951 (2022) - [i9]Linghao Song, Licheng Guo, Suhail Basalama, Yuze Chi, Robert F. Lucas, Jason Cong:
Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver. CoRR abs/2209.14350 (2022) - 2021
- [b1]Yuze Chi:
Design Automation and Optimization for Memory-Bound Application Accelerators. University of California, Los Angeles, USA, 2021 - [c15]Yuze Chi, Licheng Guo, Jason Lau
Extending High-Level Synthesis for Task-Parallel Programs. FCCM 2021: 204-213 - [c14]Licheng Guo, Yuze Chi, Jie Wang, Jason Lau
AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. FPGA 2021: 81-92 - [c13]Young-kyu Choi
HBM Connect: High-Performance HLS Interconnect for FPGA HBM. FPGA 2021: 116-126 - [c12]Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, Jason Cong:
Extending High-Level Synthesis for Task-Parallel Programs. FPGA 2021: 225 - [i8]Linghao Song, Yuze Chi, Atefeh Sohrabizadeh, Young-kyu Choi, Jason Lau, Jason Cong:
Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication. CoRR abs/2109.11081 (2021) - [i7]Linghao Song, Yuze Chi, Jason Cong:
Pyxis: An Open-Source Performance Dataset of Sparse Accelerators. CoRR abs/2110.04280 (2021) - [i6]Atefeh Sohrabizadeh, Yuze Chi, Jason Cong:
SPA-GCN: Efficient and Flexible GCN Accelerator with an Application for Graph Similarity Computation. CoRR abs/2111.05936 (2021) - [i5]Linghao Song, Yuze Chi, Licheng Guo, Jason Cong:
Serpens: A High Bandwidth Memory Based Accelerator for General-Purpose Sparse Matrix-Vector Multiplication. CoRR abs/2111.12555 (2021) - 2020
- [j2]Young-kyu Choi
FLASH: Fast, Parallel, and Accurate Simulator for HLS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4828-4841 (2020) - [c11]Yuze Chi, Jason Cong:
Exploiting Computation Reuse for Stencil Accelerators. DAC 2020: 1-6 - [c10]Licheng Guo, Jason Lau
Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. DAC 2020: 1-6 - [c9]Jiajie Li, Yuze Chi, Jason Cong:
HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration. FPGA 2020: 51-57 - [c8]Licheng Guo, Jason Lau
Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. FPGA 2020: 311 - [i4]Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, Jason Cong:
Extending High-Level Synthesis for Task-Parallel Programs. CoRR abs/2009.11389 (2020) - [i3]Young-kyu Choi, Yuze Chi, Jie Wang, Licheng Guo, Jason Cong:
When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization. CoRR abs/2010.06075 (2020)
2010 – 2019
- 2019
- [j1]Guohao Dai
GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 640-653 (2019) - [c7]Yuze Chi, Young-kyu Choi
Rapid Cycle-Accurate Simulator for High-Level Synthesis. FPGA 2019: 178-183 - [c6]Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. FPGA 2019: 242-251 - 2018
- [c5]Yuze Chi, Peipei Zhou, Jason Cong:
An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only). FPGA 2018: 286 - [c4]Yuze Chi, Jason Cong, Peng Wei, Peipei Zhou
SODA: stencil with optimized dataflow architecture. ICCAD 2018: 116 - [i2]Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang:
Rapid Cycle-Accurate Simulator for High-Level Synthesis. CoRR abs/1812.07012 (2018) - 2017
- [c3]Guohao Dai, Tianhao Huang, Yuze Chi, Ningyi Xu, Yu Wang, Huazhong Yang:
ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture. FPGA 2017: 217-226 - 2016
- [c2]Guohao Dai, Yuze Chi, Yu Wang, Huazhong Yang:
FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search. FPGA 2016: 105-110 - [c1]Yuze Chi, Guohao Dai, Yu Wang, Guangyu Sun, Guoliang Li, Huazhong Yang:
NXgraph: An efficient graph processing system on a single machine. ICDE 2016: 409-420 - 2015
- [i1]Yuze Chi, Guohao Dai, Yu Wang, Guangyu Sun, Guoliang Li, Huazhong Yang:
NXgraph: An Efficient Graph Processing System on a Single Machine. CoRR abs/1510.06916 (2015)
Coauthor Index
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