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Khosrow Hajsadeghi
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2020 – today
- 2024
- [j8]Abolfazl Roshanpanah
, Pooya Torkzadeh
A Novel Design of 16-bit Multi-Mode 4-Channel Time-Interleaved Delta-Sigma Digital-to-Analog Converter. J. Circuits Syst. Comput. 33(14): 2450248:1-2450248:27 (2024) - 2020
- [j7]Saman Behrouzi
Predicting scientific research trends based on link prediction in keyword networks. J. Informetrics 14(4): 101079 (2020)
2010 – 2019
- 2019
- [j6]Hasan Molaei
A 5.3-ps, 8-b Time to Digital Converter Using a New Gain-Reconfigurable Time Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 352-356 (2019) - 2018
- [j5]Hasan Molaei, Khosrow Hajsadeghi, Ata Khorami:
Design of low power comparator-reduced hybrid ADC. Microelectron. J. 79: 79-90 (2018) - 2017
- [j4]Hasan Molaei, Khosrow Hajsadeghi:
A 1.6 ps 7 b time to digital converter in 0.18 µm CMOS technology. Microelectron. J. 67: 120-127 (2017) - [c11]Hengameh Bahrami, Khosrow Hajsadeghi:
Circuit design to improve security of telecommunication devices. CCWC 2017: 1-4 - [c10]Hasan Molaei, Khosrow Hajsadeghi:
A low-power comparator-reduced flash ADC using dynamic comparators. ICECS 2017: 5-8 - 2016
- [c9]Hasan Molaei, Ata Khorami, Khosrow Hajsadeghi:
A wide dynamic range low power 2× time amplifier using current subtraction scheme. ISCAS 2016: 462-465 - [c8]Hasan Molaei, Khosrow Hajsadeghi:
A low power high resolution time to digital converter for ADPLL application. MWSCAS 2016: 1-4 - 2015
- [c7]Hasan Molaei, Ata Khorami, Mohammad S. Eslampanah Sendi, Khosrow Hajsadeghi:
A four bit low power 165MS/s flash-SAR ADC for sigma-delta ADC application. ICECS 2015: 153-156 - 2014
- [j3]Mohaddeseh Koosha
Fine logarithmic adaptive soft morphological algorithm for synthetic aperture radar image segmentation. IET Image Process. 8(2): 90-102 (2014) - [j2]Roghayeh Saeidi
A Subthreshold Symmetric SRAM Cell With High Read Stability. IEEE Trans. Circuits Syst. II Express Briefs 61-II(1): 26-30 (2014) - [j1]Roghayeh Saeidi
Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3386-3393 (2014) - [c6]Vahid Khojasteh Lazarjan, Khosrow Hajsadeghi:
12 bits, 40MS/s, low power pipelined SAR ADC. MWSCAS 2014: 841-844 - 2013
- [c5]Sina Hassanzadeh, Milad Zamani, Khosrow Hajsadeghi, Roghayeh Saeidi:
A novel low power 8T-cell sub-threshold SRAM with improved read-SNM. DTIS 2013: 35-38 - [c4]Milad Zamani, Sina Hassanzadeh, Khosrow Hajsadeghi, Roghayeh Saeidi:
A 32kb 90nm 9T-cell sub-threshold SRAM with improved read and write SNM. DTIS 2013: 104-107 - 2012
- [c3]Mehdi Noormohammadi, Vahid Khojasteh Lazarjan
New Operational Transconductance Amplifiers using current boosting. MWSCAS 2012: 109-112 - 2011
- [c2]Roghayeh Saeidi
A subthreshold dynamic read SRAM (DRSRAM) based on dynamic stability criteria. ISCAS 2011: 61-64
2000 – 2009
- 2008
- [c1]Amirehsan Behradfar, Saeed Zeinolabedinzadeh, Khosrow Hajsadeghi:
A clock boosting scheme for low voltage circuits. ICECS 2008: 21-24
Coauthor Index
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last updated on 2024-09-21 23:40 CEST by the dblp team
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