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C. Mukherjee 0001
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- affiliation: University of Bordeaux, Talence, France
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2020 – today
- 2024
- [c18]Ian O'Connor, Sara Mannaa, Alberto Bosio, Bastien Deveautour, Damien Deleruyelle, Tetiana Obukhova, Cédric Marchand, Jens Trommer, Çigdem Çakirlar, Bruno Neckel Wesling, Thomas Mikolajick, Oskar Baumgartner, Mischa Thesberg, David Pirker, Christoph Lenz, Zlatan Stanojevic, Markus Karner, Guilhem Larrieu, Sylvain Pelloquin, Konstantinous Moustakas, Jonas Müller, Giovanni Ansaloni, Alireza Amirshahi, David Atienza, Jean-Luc Rouas, Leila Ben Letaifa, Georgeta Bordeall, Charles Brazier, Chhandak Mukherjee, Marina Deng, Yifan Wang, Marc François, Houssem Rezgui
, Reveil Lucas, Cristell Maneux:
FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation. DATE 2024: 1-6 - 2023
- [j3]C. Mukherjee
SPICE Modeling in Verilog-A for Photo-Response in UTC-Photodiodes Targeting Beyond-5G Circuit Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 3045-3052 (2023) - [j2]Nil Davy
InP DHBT Analytical Modeling: Toward THz Transistors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4102-4111 (2023) - [c17]Yifan Wang, Chhandak Mukherjee, Houssem Rezgui, Marina Deng, Cristell Maneux, Sara Mannaa, Ian O'Connor, Jonas Müller, Sylvain Pelloquin, Guilhem Larrieu:
Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design. ESSDERC 2023: 57-60 - 2022
- [c16]Nil Davy
InP DHBT test structure optimization towards 110 GHz characterization. ESSDERC 2022: 320-323 - [c15]Arnaud Poittevin, Ian O'Connor, Cédric Marchand, Alberto Bosio, Cristell Maneux, Chhandak Mukherjee, Guilhem Larrieu, Abhishek Kumar:
A Logic Cell Design and routing Methodology Specific to VNWFET. NEWCAS 2022: 460-464 - [c14]Lucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng
Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors. VLSI-SoC 2022: 1-2 - 2021
- [c13]Nil Davy
0.4-μm InP/InGaAs DHBT with a 380-GHz ${f_{T}}$, > 600-GHz $f_{\max}$ and BVCE0 > 4.5 V. BCICTS 2021: 1-4 - [c12]Marina Deng
InP DHBT Characterization up to 500 GHz and Compact Model Validation Towards THz Circuit Design. BCICTS 2021: 1-4 - [c11]Sébastien Fregonese, Chhandak Mukherjee, Holger Rücker, Pascal Chevalier, Gerhard Fischer, Didier Céli, Marina Deng
Electro-Thermal Limitations and Device Degradation of SiGe HBTs with Emphasis on Circuit Performance. BCICTS 2021: 1-7 - [c10]C. Mukherjee, Marine Couret, Cristell Maneux, Didier Céli:
Impact of Hot Carrier Degradation on the Performances of Current Mirrors based on a 55 nm BiCMOS Integrated Circuit Technology. ESSDERC 2021: 251-254 - 2020
- [c9]Chhandak Mukherjee, Marina Deng
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. VLSI-SOC 2020: 76-81 - [c8]Arnaud Poittevin, Chhandak Mukherjee, Ian O'Connor, Cristell Maneux, Guilhem Larrieu, Marina Deng
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. VLSI-SoC (Selected Papers) 2020: 301-321 - [i1]C. Mukherjee, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu:
3D logic cells design and results based on Vertical NWFET technology including tied compact model. CoRR abs/2005.14039 (2020)
2010 – 2019
- 2019
- [c7]Chhandak Mukherjee, Patrick Mounaix, Cristell Maneux, Michele Natrella, James Seddon
First Uni-Traveling Carrier Photodiode Compact Model Enabling Future Terahertz Communication System Design. ESSDERC 2019: 150-153 - 2017
- [j1]C. Mukherjee
Random telegraph noise in SiGe HBTs: Reliability analysis close to SOA limit. Microelectron. Reliab. 73: 146-152 (2017) - [c6]Chhandak Mukherjee
1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors. ESSDERC 2017: 34-37 - 2016
- [c5]Jorgue Daniel Aguirre Morales, Sébastien Fregonese, C. Mukherjee
Physics-based electrical compact model for monolayer Graphene FETs. ESSDERC 2016: 240-243 - [c4]C. Mukherjee
Comprehensive study of random telegraph noise in base and collector of advanced SiGe HBT: Bias, geometry and trap locations. ESSDERC 2016: 260-263 - 2015
- [c3]C. Mukherjee
Characterization and modeling of low-frequency noise in CVD-grown graphene FETs. ESSDERC 2015: 176-179 - [c2]Jorgue Daniel Aguirre Morales, Sébastien Fregonese, C. Mukherjee
A new physics-based compact model for Bilayer Graphene Field-Effect Transistors. ESSDERC 2015: 180-183 - 2014
- [c1]C. Mukherjee
Qualitative assessment of epitaxial graphene FETs on SiC substrates via pulsed measurements and temperature variation. ESSDERC 2014: 305-308
Coauthor Index
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