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Hyman Shanan
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2020 – today
- 2022
- [c6]Hyman Shanan, Declan Dalton, Vamshi Chillara, Pablo Dato:
A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter, -120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5ns and 2μs Chirp Settling Time. ISSCC 2022: 146-148
2010 – 2019
- 2019
- [c5]Salvatore Galeone, Michael Peter Kennedy, Karim Ahmed, Hyman Shanan, Mike Keaveney:
An Eight-Phase 40GHz RTWO in 28nm CMOS with Phase Noise Reduction Via Head and Tail Filtering. ICECS 2019: 306-309 - 2014
- [j2]Michael Peter Kennedy
, Hongjia Mo, Brian Fitzgibbon, Austin Harney, Hyman Shanan, Mike Keaveney:
0.3-4.3 GHz Frequency-Accurate Fractional-N Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital Δ-Σ Modulator-Based Divider Controller. IEEE J. Solid State Circuits 49(7): 1595-1605 (2014) - 2013
- [c4]Michael Peter Kennedy, Brian Fitzgibbon, Austin Harney, Hyman Shanan, Mike Keaveney:
High speed, high accuracy fractional-N frequency synthesizer using nested mixed-radix digital Δ-Σ modulators. ESSCIRC 2013: 245-248
2000 – 2009
- 2009
- [j1]Guido Retz, Hyman Shanan, Kenneth Mulvaney, Shane O'Mahony, Miguel Chanca, Pat Crowley, Charley Billon, Muhammad Kalimuddin Khan, Jesus Javier Lopez Orive, Philip Quinlan:
Radio transceivers for wireless personal area networks using IEEE802.15.4. IEEE Commun. Mag. 47(9): 150-158 (2009) - [c3]Guido Retz, Hyman Shanan, Kenneth Mulvaney, Kenneth O'Mahony, Miguel Chanca, Pat Crowley, Charley Billon, Muhammad Kalimuddin Khan, Philip Quinlan:
A highly integrated low-power 2.4GHz transceiver using a direct-conversion diversity receiver in 0.18µm CMOS for IEEE802.15.4 WPAN. ISSCC 2009: 414-415 - [c2]Hyman Shanan, Guido Retz, Kenneth Mulvaney, Philip Quinlan:
A 2.4GHz 2Mb/s versatile PLL-based transmitter using digital pre-emphasis and auto calibration in 0.18µm CMOS for WPAN. ISSCC 2009: 420-421 - 2004
- [c1]Hyman Shanan, Michael Peter Kennedy:
A technique to reduce flicker noise up-conversion in CMOS LC voltage-controlled oscillators. ESSCIRC 2004: 123-126
Coauthor Index
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