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William John Bainbridge
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2010 – 2019
- 2012
- [c8]Wei Song
, Doug A. Edwards, Jim D. Garside, William J. Bainbridge:
Area efficient asynchronous SDM routers using 2-stage Clos switches. DATE 2012: 1495-1500
2000 – 2009
- 2009
- [c7]William John Bainbridge, Sean James Salisbury:
Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links. ASYNC 2009: 35-44 - 2004
- [c6]W. J. Bainbridge, Luis A. Plana
The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip. DATE 2004: 274-279 - 2003
- [j2]Luis A. Plana
SPA - a secure Amulet core for smartcard applications. Microprocess. Microsystems 27(9): 431-446 (2003) - [c5]W. J. Bainbridge, William B. Toms, David A. Edwards, Stephen B. Furber
Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes. ASYNC 2003: 132-140 - 2002
- [c4]W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside
SPA - A Synthesisable Amulet Core for Smartcard pplications. ASYNC 2002: 201-210 - 2001
- [c3]W. J. Bainbridge, Stephen B. Furber
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding. ASYNC 2001: 118-126 - 2000
- [j1]W. J. Bainbridge, Stephen B. Furber
MARBLE: an asynchronous on-chip macrocell bus. Microprocess. Microsystems 24(4): 213-222 (2000) - [c2]Jim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, Siamak Mohammadi
AMULET3i - An Asynchronous System-on-Chip. ASYNC 2000: 162-175
1990 – 1999
- 1998
- [c1]W. J. Bainbridge, Stephen B. Furber:
Asynchronous Macrocell Interconnect using MARBLE. ASYNC 1998: 122-132
Coauthor Index
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