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Ren-Shuo Liu
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2020 – today
- 2024
- [j20]Hung-Hsi Hsu
, Tai-Hao Wen, Wei-Hsing Huang, Win-San Khwa, Yun-Chen Lo
A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme. IEEE J. Solid State Circuits 59(1): 116-127 (2024) - [j19]Ping-Chun Wu, Jian-Wei Su
A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips. IEEE J. Solid State Circuits 59(1): 196-207 (2024) - [j18]De-Qi You
An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices. IEEE J. Solid State Circuits 59(1): 219-230 (2024) - [j17]Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li
An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips. IEEE J. Solid State Circuits 59(7): 2297-2309 (2024) - [j16]Yun-Chen Lo
ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory. IEEE Trans. Computers 73(9): 2136-2149 (2024) - [j15]Jian-Wei Su
8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2304-2308 (2024) - [c49]Win-San Khwa, Ping-Chun Wu, Jui-Jen Wu, Jian-Wei Su, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices. ISSCC 2024: 568-570 - [c48]Tai-Hao Wen, Hung-Hsi Hsu, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsih Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices. ISSCC 2024: 580-582 - [c47]De-Qi You, Win-San Khwa, Jui-Jen Wu, Chuan-Jia Jhang, Guan-Yi Lin, Po-Jung Chen, Ting-Chien Chiu, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j14]Yun-Chen Lo
LV: Latency-Versatile Floating-Point Engine for High-Performance Deep Neural Networks. IEEE Comput. Archit. Lett. 22(2): 125-128 (2023) - [j13]Je-Min Hung, Tai-Hao Wen, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh
8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices. IEEE J. Solid State Circuits 58(1): 303-315 (2023) - [j12]Jian-Wei Su
A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. IEEE J. Solid State Circuits 58(3): 877-892 (2023) - [j11]Min-Yang Chiu
A Multimode Vision Sensor With Temporal Contrast Pixel and Column-Parallel Local Binary Pattern Extraction for Dynamic Depth Sensing Using Stereo Vision. IEEE J. Solid State Circuits 58(10): 2767-2777 (2023) - [j10]Tzu-Hsiang Hsu
A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification. IEEE J. Solid State Circuits 58(11): 3266-3274 (2023) - [j9]Jun-Shen Wu
SG-Float: Achieving Memory Access and Computing Power Reduction Using Self-Gating Float in CNNs. ACM Trans. Embed. Comput. Syst. 22(6): 101:1-101:22 (2023) - [c46]Yun-Chen Lo, Ren-Shuo Liu:
Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference. DAC 2023: 1-6 - [c45]Yun-Chen Lo, Ren-Shuo Liu:
Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture. DAC 2023: 1-6 - [c44]Yu-Chih Tsai, Wen-Chien Ting, Chia-Chun Wang, Chia-Cheng Chang, Ren-Shuo Liu:
Built-in Self-Test and Built-in Self-Repair Strategies Without Golden Signature for Computing in Memory. DATE 2023: 1-6 - [c43]Jun-Shen Wu, Ren-Shuo Liu:
FM-P2L: An Algorithm Hardware Co-design of Fixed-Point MSBs with Power-of-2 LSBs in CNN Accelerators. ICCD 2023: 407-414 - [c42]Chia-Chun Wang
Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators. ICCD 2023: 515-522 - [c41]Yun-Chen Lo, Chia-Chun Wang, Ren-Shuo Liu:
BICEP: Exploiting Bitline Inversion for Efficient Operation-Unit-Based Compute-in-Memory Architecture: No Retraining Needed! ICCD 2023: 531-534 - [c40]Yu-Chih Tsai, Chung-Yueh Liu, Chia-Chun Wang, Tsen-Wei Hsu, Ren-Shuo Liu:
CNN Inference Accelerators with Adjustable Feature Map Compression Ratios. ICCD 2023: 631-634 - [c39]Yun-Chen Lo, Tse-Kuang Lee, Ren-Shuo Liu:
Block and Subword-Scaling Floating-Point (BSFP) : An Efficient Non-Uniform Quantization For Low Precision Inference. ICLR 2023 - [c38]Ping-Chun Wu, Jian-Wei Su
A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices. ISSCC 2023: 126-127 - [c37]Wei-Hsing Huang, Tai-Hao Wen, Je-Min Hung, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Hung-Hsi Hsu, Yu-Hsiang Chin, Yu-Chiao Chen, Chuna-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W. ISSCC 2023: 258-259 - [c36]Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, De-Qi You, Fang-Yi Chen, Andrew Lee, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A 22nm 8Mb STT-MRAM Near-Memory-Computing Macro with 8b-Precision and 46.4-160.1TOPS/W for Edge-AI Devices. ISSCC 2023: 496-497 - [c35]Yun-Chen Lo
Bucket Getter: A Bucket-based Processing Engine for Low-bit Block Floating Point (BFP) DNNs. MICRO 2023: 1002-1015 - [c34]Tai-Hao Wen, Je-Min Hung, Hung-Hsi Hsu, Yuan Wu, Fu-Chun Chang, Chung-Yuan Li, Chih-Han Chien, Chin-I Su, Win-San Khwa, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j8]Jian-Wei Su
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. IEEE J. Solid State Circuits 57(2): 609-624 (2022) - [c33]Yun-Chen Lo, Chih-Chen Yeh, Jun-Shen Wu, Chia-Chun Wang, Yu-Chih Tsai, Wen-Chien Ting, Ren-Shuo Liu:
ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators. ICCAD 2022: 86:1-86:9 - [c32]Tzu-Hsiang Hsu, Guan-Cheng Chen, Yi-Ren Chen, Chung-Chuan Lo, Ren-Shuo Liu, Meng-Fan Chang, Kea-Tiong Tang, Chih-Cheng Hsieh:
A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification. ISSCC 2022: 1-3 - [c31]Je-Min Hung, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Tai-Hao Wen, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices. ISSCC 2022: 1-3 - [c30]Ping-Chun Wu, Jian-Wei Su
A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. ISSCC 2022: 1-3 - [c29]Yen-Cheng Chiu, Chia-Sheng Yang, Shih-Hsih Teng, Hsiao-Yu Huang, Fu-Chun Chang, Yuan Wu, Yu-An Chien, Fang-Ling Hsieh, Chung-Yuan Li, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, Chung-Chuan Lo, Win-San Khwa, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chieh-Pu Lo, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations. ISSCC 2022: 178-180 - 2021
- [j7]Tzu-Hsiang Hsu
A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction. IEEE J. Solid State Circuits 56(5): 1588-1596 (2021) - [j6]Tzu-Hsiang Hsu
A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel. IEEE J. Solid State Circuits 56(8): 2516-2524 (2021) - [j5]Xin Si
A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. IEEE J. Solid State Circuits 56(9): 2817-2831 (2021) - [c28]Hsin-Yu Wu, Wei-Tse Kao, Harrison Hao-Yu Ku, Cheng-Te Wang, Chih-Cheng Hsieh, Ren-Shuo Liu, Kea-Tiong Tang, Chung-Chuan Lo:
A Bio-Inspired Motion Detection Circuit Model for the Computation of Optical Flow: The Spatial-Temporal Filtering Reichardt Model. AICAS 2021: 1-4 - [c27]Wen-Chieh Wu, Chen-Fu Yeh, Alexander James White
Integer Quadratic Integrate-and-Fire (IQIF): A Neuron Model for Digital Neuromorphic Systems. AICAS 2021: 1-4 - [c26]Jun-Shen Wu, Chi-En Wang, Ren-Shuo Liu:
Value-Aware Error Detection and Correction for SRAM Buffers in Low-Bitwidth, Floating-Point CNN Accelerators. ASP-DAC 2021: 242-247 - [c25]Cheng-Xin Xue, Je-Min Hung, Hui-Yao Kao, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Peng Chen, Ta-Wei Liu, Chuan-Jia Jhang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices. ISSCC 2021: 245-247 - [c24]Jian-Wei Su
16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips. ISSCC 2021: 250-252 - 2020
- [j4]Xin Si
A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. IEEE J. Solid State Circuits 55(1): 189-202 (2020) - [j3]Cheng-Xin Xue, Ting-Wei Chang, Tung-Cheng Chang, Hui-Yao Kao, Yen-Cheng Chiu, Chun-Ying Lee, Ya-Chin King
Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors. IEEE J. Solid State Circuits 55(1): 203-215 (2020) - [j2]Yen-Cheng Chiu, Zhixiao Zhang, Jia-Jing Chen, Xin Si
A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors. IEEE J. Solid State Circuits 55(10): 2790-2801 (2020) - [c23]Tzu-Hsiang Hsu, Yen-Kai Chen, Jun-Shen Wu, Wen-Chien Ting, Cheng-Te Wang, Chen-Fu Yeh, Syuan-Hao Sie, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh:
5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel. ISSCC 2020: 110-112 - [c22]Jian-Wei Su
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. ISSCC 2020: 240-242 - [c21]Cheng-Xin Xue, Tsung-Yuan Huang, Je-Syu Liu, Ting-Wei Chang, Hui-Yao Kao, Jing-Hong Wang, Ta-Wei Liu, Shih-Ying Wei, Sheng-Po Huang, Wei-Chen Wei, Yi-Ren Chen, Tzu-Hsiang Hsu, Yen-Kai Chen, Yun-Chen Lo, Tai-Hsing Wen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices. ISSCC 2020: 244-246 - [c20]Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su
15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. ISSCC 2020: 246-248
2010 – 2019
- 2019
- [c19]Cheng-Hsuan Cheng, Ren-Shuo Liu:
AIP: Saving the DRAM Access Energy of CNNs Using Approximate Inner Products. AICAS 2019: 311-315 - [c18]Tzu-Hsiang Hsu
A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction. A-SSCC 2019: 33-34 - [c17]Zhixiao Zhang, Jia-Jing Chen, Xin Si, Yung-Ning Tu, Jian-Wei Su
A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors. A-SSCC 2019: 217-218 - [c16]Yun-Chen Lo, Yu-Chun Kuo, Yun-Sheng Chang, Jian-Hao Huang, Jun-Shen Wu, Wen-Chien Ting, Tai-Hsing Wen, Ren-Shuo Liu:
Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN). ESSCIRC 2019: 241-244 - [c15]Cheng-Xin Xue, Wei-Hao Chen, Je-Syu Liu, Jia-Fang Li, Wei-Yu Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Ting-Wei Chang, Tung-Cheng Chang, Tsung-Yuan Huang, Hui-Yao Kao, Shih-Ying Wei, Yen-Cheng Chiu, Chun-Ying Lee, Chung-Chuan Lo, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors. ISSCC 2019: 388-390 - [c14]Xin Si
A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. ISSCC 2019: 396-398 - [c13]Yu-Chun Kuo, Ruei-Fong Chiu, Ren-Shuo Liu:
Long-Term JPEG Data Protection and Recovery for NAND Flash-Based Solid-State Storage. MSST 2019: 141-147 - [c12]Yun-Sheng Chang, Ren-Shuo Liu:
OPTR: Order-Preserving Translation and Recovery Design for SSDs with a Standard Block Device Interface. USENIX ATC 2019: 1009-1024 - [c11]Kea-Tiong Tang, Wei-Chen Wei, Zuo-Wei Yeh, Tzu-Hsiang Hsu, Yen-Cheng Chiu, Cheng-Xin Xue, Yu-Chun Kuo, Tai-Hsing Wen, Mon-Shu Ho, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Meng-Fan Chang:
Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices. VLSI Circuits 2019: 166- - 2018
- [c10]Jian-Hao Huang, Ren-Shuo Liu:
DI-SSD: Desymmetrized interconnection architecture and dynamic timing calibration for solid-state drives. ASP-DAC 2018: 34-39 - [c9]Pin-Yi Li, Cheng-Han Yang, Wei-Hao Chen, Jian-Hao Huang, Wei-Chen Wei, Je-Syu Liu, Wei-Yu Lin, Tzu-Hsiang Hsu, Chih-Cheng Hsieh, Ren-Shuo Liu, Meng-Fan Chang, Kea-Tiong Tang:
A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array. BioCAS 2018: 1-4 - [c8]Wei-Hao Chen, Kai-Xiang Li, Wei-Yu Lin, Kuo-Hsiang Hsu, Pin-Yi Li, Cheng-Han Yang, Cheng-Xin Xue, En-Yu Yang, Yen-Kai Chen, Yun-Sheng Chang, Tzu-Hsiang Hsu, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors. ISSCC 2018: 494-496 - [c7]Ren-Shuo Liu, Yun-Chen Lo, Yuan-Chun Luo, Chih-Yu Shen, Cheng-Ju Lee:
DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout. VLSI-DAT 2018: 1-4 - 2017
- [c6]Ren-Shuo Liu, Yun-Sheng Chang, Chih-Wen Hung:
VST: A virtual stress testing framework for discovering bugs in SSD flash-translation layers. ICCAD 2017: 283-290 - 2016
- [j1]Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang
Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality. IEEE Trans. Computers 65(4): 1090-1102 (2016) - 2014
- [c5]Ren-Shuo Liu, De-Yu Shen, Chia-Lin Yang
NVM duet: unified working memory and persistent store architecture. ASPLOS 2014: 455-470 - [c4]Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs. DAC 2014: 145:1-145:6 - 2013
- [c3]Ren-Shuo Liu, Chia-Lin Yang
DuraCache: a durable SSD cache using MLC NAND flash. DAC 2013: 166:1-166:6 - 2012
- [c2]Ren-Shuo Liu, Chia-Lin Yang, Wei Wu:
Optimizing NAND flash-based SSDs via retention relaxation. FAST 2012: 11 - 2010
- [c1]Ren-Shuo Liu, Yun-Cheng Tsai, Chia-Lin Yang
Parallelization and characterization of GARCH option pricing on GPUs. IISWC 2010: 1-10
Coauthor Index
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