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Zhengfan Xia
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2020 – today
- 2023
- [j4]Rahul Gulve
, Navid Sarhangnejad
39 000-Subexposures/s Dual-ADC CMOS Image Sensor With Dual-Tap Coded-Exposure Pixels for Single-Shot HDR and 3-D Computational Imaging. IEEE J. Solid State Circuits 58(11): 3150-3163 (2023) - 2022
- [c5]Rahul Gulve, Navid Sarhangnejad, Gairik Dutta, Motasem Sakr, Don Nguyen, Roberto Rangel, Wenzheng Chen, Zhengfan Xia, Mian Wei, Nikita Gusev, Esther Y. H. Lin, Xiaonong Sun, Leo Hanxu, Nikola Katic, Ameer Abdelhadi, Andreas Moshovos, Kiriakos N. Kutulakos, Roman Genov:
A 39, 000 Subexposures/s CMOS Image Sensor with Dual-tap Coded-exposure Data-memory Pixel for Adaptive Single-shot Computational Imaging. VLSI Technology and Circuits 2022: 78-79
2010 – 2019
- 2019
- [j3]Navid Sarhangnejad
Dual-Tap Computational Photography Image Sensor With Per-Pixel Pipelined Digital Memory for Intra-Frame Coded Multi-Exposure. IEEE J. Solid State Circuits 54(11): 3191-3202 (2019) - [c4]Navid Sarhangnejad, Nikola Katic, Zhengfan Xia, Mian Wei, Nikita Gusev, Gairik Dutta, Rahul Gulve, Harel Haim, Manuel Moreno Garcia, David Stoppa, Kiriakos N. Kutulakos, Roman Genov:
Dual-Tap Pipelined-Code-Memory Coded-Exposure-Pixel CMOS Image Sensor for Multi-Exposure Single-Frame Computational Imaging. ISSCC 2019: 102-104 - 2018
- [c3]Mian Wei, Navid Sarhangnejad, Zhengfan Xia, Nikita Gusev, Nikola Katic, Roman Genov, Kiriakos N. Kutulakos:
Coded Two-Bucket Cameras for Computer Vision. ECCV (3) 2018: 55-73 - [c2]Yuichi Komano
Efficient and Secure Firmware Update/Rollback Method for Vehicular Devices. ISPEC 2018: 455-467 - 2015
- [j2]Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama:
Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 619-630 (2015) - 2012
- [j1]Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama:
Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates. IEICE Trans. Electron. 95-C(8): 1434-1443 (2012) - [c1]Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama:
Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit. ISCAS 2012: 3017-3020
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