default search action
Cong Shi 0003
Person information
- affiliation: Chongqing University, School of Microelectronics and Communication Engineerin, China
- affiliation: Harvard Medical School, Schepens Eye Research Institute, Massachusetts Eye and Ear, Boston, MA, USA
- affiliation (PhD 2014): Tsinghua University, Beijing, China
- affiliation (PhD 2014): Chinese Academy of Sciences, Institute of Semiconductors, Beijing, China
Other persons with the same name
- Cong Shi — disambiguation page
- Cong Shi 0001
— University of Michigan, Ann Arbor, MI, USA
- Cong Shi 0002 — Beijing University of Posts and Telecommunications, MOE, Key Laboratory of Universal Wireless Communications, China
- Cong Shi 0004
- Cong Shi 0005
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
- [j27]Li Wang, Cong Shi, Shrinivas J. Pundlik, Xu Yang, Liyuan Liu, Gang Luo:
LLD-GAN: An end-to-end network for low-light image demosaicking. Displays 85: 102856 (2024) - [j26]Siyuan Wei
A Real-Time 2D/3D Perception Visual Vector Processor for 1920 × 1080 High-Resolution High-Speed Intelligent Vision Chips. IEEE Trans. Circuits Syst. I Regul. Pap. 71(2): 740-753 (2024) - [j25]Cong Shi
Ghost Reservoir: A Memory-Efficient Low-Power and Real-Time Neuromorphic Processor of Liquid State Machine With On-Chip Learning. IEEE Trans. Circuits Syst. II Express Briefs 71(10): 4526-4530 (2024) - 2023
- [j24]Cong Shi, Junxian He, Shrinivas J. Pundlik, Xichuan Zhou, Nanjian Wu, Gang Luo:
Low-cost real-time VLSI system for high-accuracy optical flow estimation using biological motion features and random forests. Sci. China Inf. Sci. 66(5) (2023) - [j23]Cong Shi, Li Wang, Haoran Gao, Min Tian
Learnable Leakage and Onset-Spiking Self-Attention in SNNs with Local Error Signals. Sensors 23(24): 9781 (2023) - [j22]Xiandong Zhao
Network Pruning for Bit-Serial Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5): 1597-1609 (2023) - [j21]Leyi Chen, Cong Shi
An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips. IEEE Trans. Circuits Syst. I Regul. Pap. 70(11): 4249-4259 (2023) - [j20]Cong Shi
An Edge Neuromorphic Hardware With Fast On-Chip Error-Triggered Learning on Compressive Sensed Spikes. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2665-2669 (2023) - [j19]Lei Kang
A 24.3 μJ/Image SNN Accelerator for DVS-Gesture With WS-LOS Dataflow and Sparse Methods. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 4226-4230 (2023) - [c19]Zhengqing Zhong, Tengxiao Wang, Haibing Wang, Zhihua Zhou, Junxian He, Fang Tang, Xichuan Zhou, Shuangming Yu, Liyuan Liu, Nanjian Wu, Min Tian, Cong Shi:
Live Demonstration: Face Recognition at The Edge Using Fast On-Chip Deep Learning Neuromorphic Chip. AICAS 2023: 1-2 - [c18]Tengxiao Wang, Min Tian, Zhengqing Zhong, Haibing Wang, Junxian He, Fang Tang, Xichuan Zhou, Shuangming Yu, Nanjian Wu, Liyuan Liu, Cong Shi:
MorphBungee: A 65nm 7.2mm2 27μJ/image Digital Edge Neuromorphic Chip with On-Chip 802 Frame/s Multi-Layer Spiking Neural Network Learning. A-SSCC 2023: 1-3 - [c17]Fuming Lei, Xu Yang, Jian Liu, Nanjian Wu, Cong Shi, Runjiang Dou, Liyuan Liu:
A Lightweight Integer-STBP On-Chip Learning Method of Spiking Neural Networks For Edge Processors. ICTA 2023: 1-2 - 2022
- [j18]Haibing Wang, Zhen He
TripleBrain: A Compact Neuromorphic Hardware Core With Fast On-Chip Self-Organizing and Reinforcement Spike-Timing Dependent Plasticity. IEEE Trans. Biomed. Circuits Syst. 16(4): 636-650 (2022) - [j17]Zhen He, Cong Shi
A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1657-1661 (2022) - [c16]Leyi Chen, Junxian He, Jianyi Yu, Haibing Wang, Jing Lu, Liyuan Liu, Nanjian Wu, Cong Shi, Min Tian:
An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips. APCCAS 2022: 1-5 - [c15]Tengxiao Wang, Haibing Wang, Junxian He, Zhengqing Zhong, Fang Tang, Xichuan Zhou, Shuangming Yu, Liyuan Liu, Nanjian Wu, Min Tian, Cong Shi:
MorphBungee: An Edge Neuromorphic Chip for High-Accuracy On-Chip Learning of Multiple-Layer Spiking Neural Networks. BioCAS 2022: 255-259 - [c14]Min Tian, Jing Lu, Haoran Gao, Haibing Wang, Jianyi Yu, Cong Shi:
A Lightweight Spiking GAN Model for Memristor-centric Silicon Circuit with On-chip Reinforcement Adversarial Learning. ISCAS 2022: 3388-3392 - 2021
- [j16]Tengxiao Wang, Cong Shi, Xichuan Zhou, Yingcheng Lin, Junxian He, Ping Gan, Ping Li, Ying Wang, Liyuan Liu, Nanjian Wu, Gang Luo
CompSNN: A lightweight spiking neural network based on spatiotemporally compressive spike features. Neurocomputing 425: 96-106 (2021) - [j15]Kai Qin, Fangyuan Ge, Yingjun Zhao, Ling Zhu, Ming Li
Hapke Data Augmentation for Deep Learning-Based Hyperspectral Data Analysis With Limited Samples. IEEE Geosci. Remote. Sens. Lett. 18(5): 886-890 (2021) - [j14]Ling Zhang, Jing Yang, Cong Shi, Yingcheng Lin
A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps. Sensors 21(18): 6006 (2021) - [j13]Ying Wang
An Edge 3D CNN Accelerator for Low-Power Activity Recognition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 918-930 (2021) - [j12]Wei He, Jie Zhang, Yingcheng Lin, Xichuan Zhou
A Low-Cost High-Speed Object Tracking VLSI System Based on Unified Textural and Dynamic Compressive Features. IEEE Trans. Circuits Syst. II Express Briefs 68(3): 1013-1017 (2021) - [j11]Cong Shi
DeepTempo: A Hardware-Friendly Direct Feedback Alignment Multi-Layer Tempotron Learning Rule for Deep Spiking Neural Networks. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1581-1585 (2021) - [c13]Xichuan Zhou, Kui Liu, Cong Shi, Haijun Liu, Ji Liu:
Optimizing Information Theory Based Bitwise Bottlenecks for Efficient Mixed-Precision Activation Quantization. AAAI 2021: 3590-3598 - [c12]Cong Shi, Jing Lu, Ying Wang, Ping Li, Min Tian:
Exploiting Memristors for Neuromorphic Reinforcement Learning. AICAS 2021: 1-4 - [c11]Yingcheng Lin, Rui Li, Wei He, Xichuan Zhou, Junxian He, Ping Li, Liyuan Liu, Nanjian Wu, Cong Shi:
A Pixel-Parallel Array Processor without Computational Logic for Computational Image Sensors. ICTA 2021: 51-52 - [c10]Haibing Wang, Zhen He, Jinsong Rao, Tengxiao Wang, Junxian He, Min Tian, Xichuan Zhou, Liyuan Liu, Nanjian Wu, Cong Shi:
TripleBrain: An Edge Neuromorphic Architecture for High-accuracy Single-layer Spiking Neural Network with On-chip Self-organizing and Reinforcement Learning. ICTA 2021: 88-89 - [c9]Xichuan Zhou, Zhenghua Zhou, Zhengqing Zhong, Jianyi Yu, Tengxiao Wang, Min Tian, Ying Jiang, Cong Shi:
A Heterogeneous Spiking Neural Network for Computationally Efficient Face Recognition. ISCAS 2021: 1-5 - 2020
- [j10]Wei He, Jinguo Huang, Tengxiao Wang, Yingcheng Lin
A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification. Sensors 20(17): 4715 (2020) - [c8]Xiandong Zhao, Ying Wang, Cheng Liu
BitPruner: Network Pruning for Bit-serial Accelerators. DAC 2020: 1-6 - [c7]Xichuan Zhou, Yicong Peng, Chunqiao Long, Fengbo Ren, Cong Shi:
MoNet3D: Towards Accurate Monocular 3D Object Localization in Real Time. ICML 2020: 11503-11512 - [c6]Yingcheng Lin, Rui Li, Wei He, Xichuan Zhou, Junxian He, Ping Li, Ying Jiang, Liyuan Liu, Nanjian Wu, Cong Shi:
A High-speed Low-cost CNN Inference Accelerator for Depthwise Separable Convolution. ICTA 2020: 63-64 - [i2]Xichuan Zhou, Kui Liu, Cong Shi, Haijun Liu, Ji Liu:
Neural Network Activation Quantization with Bitwise Information Bottlenecks. CoRR abs/2006.05210 (2020) - [i1]Xichuan Zhou, Yicong Peng, Chunqiao Long, Fengbo Ren, Cong Shi:
MoNet3D: Towards Accurate Monocular 3D Object Localization in Real Time. CoRR abs/2006.16007 (2020)
2010 – 2019
- 2019
- [j9]Cong Shi
A Hardware-Friendly Optical Flow-Based Time-to-Collision Estimation Algorithm. Sensors 19(4): 807 (2019) - [c5]Junxian He, Xichuan Zhou, Yingcheng Lin, Chonglei Sun, Cong Shi, Nanjian Wu, Gang Luo
20, 000-fps Visual Motion Magnification on Pixel-parallel Vision Chip. ASICON 2019: 1-4 - [c4]Jinguo Huang, Yingcheng Lin, Wei He, Xichuan Zhou, Cong Shi, Nanjian Wu, Gang Luo
High-speed Classification of AER Data Based on a Low-cost Hardware System. ASICON 2019: 1-4 - [c3]Yongchen Wang, Ying Wang, Huawei Li, Cong Shi, Xiaowei Li
Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis. DAC 2019: 210 - 2018
- [j8]Cong Shi
Exploiting Lightweight Statistical Learning for Event-Based Vision Processing. IEEE Access 6: 19396-19406 (2018) - [j7]Cong Shi
A Streaming Motion Magnification Core for Smart Image Sensors. IEEE Trans. Circuits Syst. II Express Briefs 65-II(9): 1229-1233 (2018) - [j6]Cong Shi
A Compact VLSI System for Bio-Inspired Visual Motion Estimation. IEEE Trans. Circuits Syst. Video Technol. 28(4): 1021-1036 (2018) - 2015
- [j5]Yangfan Zhou
A low power global shutter pixel with extended FD voltage swing range for large format high speed CMOS image sensor. Sci. China Inf. Sci. 58(4): 1-10 (2015) - 2014
- [j4]Yangfan Zhou
A high speed 1000 fps CMOS image sensor with low noise global shutter pixels. Sci. China Inf. Sci. 57(4): 1-8 (2014) - [j3]Cong Shi, Jie Yang, Nanjian Wu, ZhiHua Wang:
A high speed multi-level-parallel array processor for vision chips. Sci. China Inf. Sci. 57(6): 1-12 (2014) - [j2]Cong Shi, Jie Yang, Liyuan Liu, Nanjian Wu, ZhiHua Wang:
A massively parallel keypoint detection and description (MP-KDD) algorithm for high-speed vision chip. Sci. China Inf. Sci. 57(10): 1-12 (2014) - [j1]Cong Shi, Jie Yang, Ye Han, Zhongxiang Cao, Qi Qin, Liyuan Liu, Nanjian Wu, Zhihua Wang:
A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network. IEEE J. Solid State Circuits 49(9): 2067-2082 (2014) - [c2]Cong Shi, Jie Yang, Ye Han, Zhongxiang Cao, Qi Qin, Liyuan Liu, Nanjian Wu, Zhihua Wang:
7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network. ISSCC 2014: 128-129 - 2013
- [c1]Zhe Chen, Jie Yang, Cong Shi, Nanjian Wu:
A novel architecture of local memory for programmable SIMD vision chip. ASICON 2013: 1-4
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-11-04 20:43 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: