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Valavan Manohararajah
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2010 – 2019
- 2016
- [c8]David M. Lewis, Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken:
The Stratix™ 10 Highly Pipelined FPGA Architecture. FPGA 2016: 159-168
2000 – 2009
- 2007
- [j3]Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh
, Stephen Dean Brown:
Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. Very Large Scale Integr. Syst. 15(8): 895-903 (2007) - 2006
- [j2]Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic:
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2331-2340 (2006) - [c7]Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic:
Adaptive FPGAs: High-Level Architecture and a Synthesis Method. FPL 2006: 1-8 - [c6]Gordon R. Chiu, Deshanand P. Singh
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD 2006: 135-142 - [c5]Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP 2006: 3-8 - 2005
- [c4]Deshanand P. Singh
Two-stage physical synthesis for FPGAs. CICC 2005: 171-178 - [c3]Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown:
Incremental retiming for FPGA physical synthesis. DAC 2005: 433-438 - [c2]Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown:
Post-Placement BDD-Based Decomposition for FPGAs. FPL 2005: 31-38 - 2002
- [c1]Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic:
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. FPL 2002: 232-241
1990 – 1999
- 1997
- [j1]Valavan Manohararajah:
Rajah: The Design of a Chess Program. J. Int. Comput. Games Assoc. 20(2): 87-91 (1997)
Coauthor Index
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