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Hiroyuki Kanaya
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2020 – today
- 2024
- [c3]Rina Takashima, Takeo Koike, Shogo Itai, Hideyuki Sugiyama, Young Min Lee, Masaru Toko, Soichiro Ono, Daisuke Watanabe, Soichi Oikawa, Katsuhiko Koi, Hiroyuki Kanaya, Masahiko Nakayama, Kohji Nakamura:
Microscopic Modeling of MgO Barrier Degradation Due to Interface Oxygen Frenkel Defects in Scaled MTJ Toward High-Density STT-MRAM. IRPS 2024: 10
2010 – 2019
- 2011
- [j3]Daisaburo Takashima, Hidehiro Shiga
, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama:
A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs. IEEE J. Solid State Circuits 46(9): 2171-2179 (2011) - 2010
- [j2]Hidehiro Shiga
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes. IEEE J. Solid State Circuits 45(1): 142-152 (2010) - [c2]Daisaburo Takashima, Hidehiro Shiga
A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM. ISSCC 2010: 262-263
2000 – 2009
- 2009
- [c1]Hidehiro Shiga
A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes. ISSCC 2009: 464-465 - 2001
- [j1]Daisaburo Takashima, Yoshiaki Takeuchi, Tadashi Miyakawa, Yasuo Itoh, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Sumiko Mano Doumae, Tohru Ozaki, Hiroyuki Kanaya, Koji Yamakawa, Iwao Kunishima, Yukihito Oowaki:
A 76-mm2 8-Mb chain ferroelectric memory. IEEE J. Solid State Circuits 36(11): 1713-1720 (2001)
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