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Microelectronics Journal, Volume 86
Volume 86, April 2019
- Linan Li, Wenqiang Ba, Wei Wang, Ling Li, Guangwei Xu, Lingfei Wang, Zhuoyu Ji, Congyan Lu, Writam Banerjee:
A physical model for dual gate a-InGaZnO thin film transistors based on multiple trapping and release mechanism. 1-6 - Soumitra Pal
, Vivek Gupta
Design of CNFET based power- and variability-aware nonvolatile RRAM cell. 7-14 - Abdullah F. Al Naim
Entanglement and physical attributes of the interaction between two SC-qubits and thermal field in the presence of a magnetic field. 15-21 - Nimrod Wald, Shahar Kvatinsky:
Understanding the influence of device, circuit and environmental variations on real processing in memristive memory using Memristor Aided Logic. 22-33 - Zhe Xue, Jin He, Ya Fang, Hao Wang, Sheng Chang, Qijun Huang, Yinxia Zhu:
A 10-Gb/s inductorless optical receiver in 0.18-μm SiGe BiCMOS. 34-39 - Archana Sunitha, Bhaskar Manickam
Co-design of on-chip loop antenna and differential class-E power amplifier at 2.4 GHz for biotelemetry applications. 40-48 - Ngoc Le Ba, Sechang Oh, Dennis Sylvester, Tony Tae-Hyoung Kim
A 256 pixel, 21.6 μW infrared gesture recognition processor for smart devices. 49-56 - Ehsan Kargaran, Danilo Manstretta
A 1.5-2.8 GHz current-mode LNTA achieving >25 dBm IIP3 and +8 dBm P-1dB gain compression. 57-64 - Emanuele Valea
Stream vs block ciphers for scan encryption. 65-76
- David Kubánek, Todd J. Freeborn
Fractional-order band-pass filter design using fractional-characteristic specimen functions. 77-86
- Xuhui Yang, Qingguo Zhou, Jinqiang Wang, Lihong Han, Fang Feng
FPGA-based approximate calculation system of General Vector Machine. 87-96
- M. Sabzi, Ali Medi
Analysis and design of multi-stage wideband LNA using simultaneously noise and impedance matching method. 97-104 - Mostafa G. Abdelmageed, Ahmed M. R. Fath El-Bab
Design and simulation of pulsatile blood flow energy harvester for powering medical devices. 105-113
- Roman Sotner, Jan Jerabek
Electronically reconfigurable two-path fractional-order PI/D controller employing constant phase blocks based on bilinear segments using CMOS modified current differencing unit. 114-129
- Zhenrong Li, Shuang Liu, Chaoyue Zhang, Yiqi Zhuang:
A 2-20 GHz SiGe HBT single-stage cascode LNA with linearity enhancement. 130-139 - Maliheh Rafiee, M. B. Ghaznavi-Ghoushchi:
Design of low-voltage shallow-depth differential source coupled logic using feedback and feedforward techniques. 140-149 - Chih-Yuan Yeh, Jung-Tang Huang, Sheng-Hsiang Tseng, Po-Chang Wu, Hann-Huei Tsai, Ying-Zong Juang:
A low-power monolithic three-axis accelerometer with automatically sensor offset compensated and interface circuit. 150-160
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