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Journal of Low Power Electronics, Volume 6
Volume 6, Number 1, April 2010
- Behnam Ghavami, Hossein Pedram, Mahtab Niknahad:
An Efficient Energy Estimation Methodology for Quasi Delay Insensitive Template-Based Asynchronous Circuits. 1-9 - Binu P. John, Abhishek Agrawal, Bob Steigerwald, Eugene B. John
:
Impact of Operating System Behavior on Battery Life. 10-17 - Ka-Ming Keung, Akhilesh Tyagi:
State Space Reconfigurability: A Low Energy Implementation Architecture for Self Modifying Finite Automata. 18-31 - Antoine Courtay, Johann Laurent, Olivier Sentieys
Spatial Switching Data Coding Technique Analysis and Improvements for Interconnect Power Consumption Optimization. 32-43 - Luca Benini
A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits. 44-55 - Sreeharsha Tavva, Dhireesha Kudithipudi:
Characterization of Variation Aware Nanoscale Static Random Access Memory Designs. 56-65 - Akshit Dayal, Peng Li, Garng M. Huang:
Robust SRAM Design via Joint Sizing and Voltage Optimization Under Dynamic Stability Constraints. 66-79 - Sudip Roy, Ajit Pal:
A New Technique for Runtime Leakage Reduction and Its Sensitivity and Parametric Yield Analysis Under Effective Channel-Length Variation. 80-92 - Alejandro Millán
Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies. 93-102 - Ramesh Vaddi
Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs. 103-114 - Guo Yu, Peng Li:
Exploring Circuit Adaptation for Yield Optimization of Low-Power All-Digital Phase-Locked Loops. 115-125 - Ka Nang Leung
A 1.9 µW Transient-Enhanced Low-Dropout Regulator with Voltage-Spike Suppression. 126-132 - Wing Yan Leung, Tsz Yin Man, Dongwei Zhang, Jin He, Mansun Chan
A High Power Switch-Mode LED Driver with an Efficient Current Sensing Scheme. 133-140 - Ka Nang Leung
RF Module Design of Passive UHF RFID Tag Implemented in CMOS 90-nm Technology. 141-149 - Nisar Ahmed, Mohammad Tehranipoor:
A Novel IR-Drop Tolerant Transition Delay Fault Test Pattern Generation Procedure. 150-159 - José Monteiro:
Selected Articles from the PATMOS 2009 Workshop. 160 - Toby Doorn, Roelof Salters:
Robust Low Power Embedded SRAM: From System Considerations to Cell Design. 161-172 - Howard Chen, Indira Nair, Benjamin Mashak:
The Effect of Dynamic Power Management on Mid-Frequency and Low-Frequency Power Supply Noise. 173-180 - Milos Krstic
Reducing Electromagnetic Interference Using Globally Asynchronous Locally Synchronous Approach. 181-191 - Paulo F. Butzen
Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits. 192-200 - Motoi Ichihashi, Hélène Lhermet, Edith Beigné
An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process. 201-210 - Armin Tajalli, Yusuf Leblebici:
Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits. 211-217 - Hossein Karimiyan Alidash, Vojin G. Oklobdzija:
Low-Power Soft Error Hardened Latch. 218-226
Volume 6, Number 2, August 2010
- Peng Rong, Massoud Pedram:
A Markovian Decision-Based Approach for Extending the Lifetime of a Network of Battery-Powered Mobile Devices by Remote Processing. 227-239 - D. Ramakrishnan, Y. L. Wu, W. B. Jone:
Design and Analysis of Location Caches in a NoC-Based Chip Multiprocessor System. 240-262 - Hailong Jiao, Volkan Kursun
Low-Leakage and Compact Registers with Easy-Sleep Mode. 263-279 - Akhilesh Kumar, Mohab Anis:
Power-Yield Enhancement for Field Programmable Gate Arrays Under Process Variations. 280-290 - Thomas Schweizer, Julio A. de Oliveira Filho, Tommy Kuhn, Wolfgang Rosenstiel:
Charge Recycling in Voltage-Dithered Circuits. 291-299 - Mallik Kandala, Haibo Wang:
Low-Power Circuit Techniques for Charge-Scaling Successive Approximation Register ADC Design. 300-310 - Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas:
Scan Shift Power Reduction by Gating Internal Nodes. 311-319 - David Coleman, Jia Di:
Analysis and Improvement of Delay-Insensitive Asynchronous Circuits Operating in Subthreshold Regime. 320-324 - Alex Bystrov
Selected Peer-Reviewed Articles from the LPonTR 2009 Workshop. 325 - Ilia Polian:
Power Supply Noise: Causes, Effects, and Testing. 326-338 - Judit Freijedo, Lucía Costas, Jorge Semião
Impact of Power Supply Voltage Variations on FPGA-Based Digital Systems Performance. 339-349 - Irith Pomeranz, Sudhakar M. Reddy:
Test Sequences with Reduced and Increased Switching Activity. 350-358 - Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed:
A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. 359-374
Volume 6, Number 3, October 2010
- Swarup Bhunia
A Special Issue on 23rd IEEE International Conference on VLSI Design, Bangalore, India, 3-7 January 2010. 375 - Sumit Ahuja, Wei Zhang, Avinash Lakshminarayana, Sandeep K. Shukla
Power Aware High Level Synthesis of Hardware Coprocessors. 376-389 - Garima Thakral, Saraju P. Mohanty, Dhiraj K. Pradhan, Elias Kougianos:
DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM. 390-400 - Bharghava Rajaram, Abinesh Ramachandran, Suresh Purini, R. Govindatajulu:
Design of Low Power Systems Using Inexact Logic Circuits. 401-414 - Vinay Saripalli, Lu Liu, Suman Datta, Vijaykrishnan Narayanan:
Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits. 415-428 - Sandeep Saini
An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. 429-435 - Koushik Chakraborty, Sanghamitra Roy
A Novel Threshold Voltage Assignment for 3D Multicore Designs. 436-446 - Hao Xu, Wen-Ben Jone, Ranga Vemuri
Tuning Vth Hopping for Aggressive Runtime Leakage Control. 447-456 - Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya:
PVT: Unified Reduction of Test Power, Volume, and Test Time Using Double-Tree Scan Architecture. 457-468
Volume 6, Number 4, December 2010
- Sohan Purohit, Marco Lanuzza
Design Space Exploration of Split-Path Data Driven Dynamic Full Adder. 469-481 - Kiran K. Chaddha, Rajeevan Chandel
Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate-Diffusion Input Technique. 482-490 - Ying Teng, Baris Taskin:
Look-Up Table Based Low Power Rotary Traveling Wave Oscillator Design Considering the Skin Effect. 491-502 - Tooraj Nikoubin, Mahdieh Grailoo, Sayyed Hasan Mozafari:
Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style. 503-512 - Ashutosh Nandi, Rajeevan Chandel
Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications. 513-520 - Maurice Meijer, José Pineda de Gyvez, Ajay Kapoor:
Ultra-Low-Power Digital Design with Body Biasing for Low Area and Performance-Efficient Operation. 521-532 - Surendra S. Rathod
Robust Double Gate FinFET Based Sense Amplifier Design Using Independent Gate Control. 533-544 - Vyasa Sai, Ajay Ogirala, Marlin H. Mickle:
Low Power Radio Frequency Identification Design Using Custom Asynchronous Passive Computer. 545-550 - Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang:
A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. 551-562 - Nadine Azémard:
Selected Peer-Reviewed Articles from the VARI 2010 Workshop. 563 - Imen Mansouri, Pascal Benoit, Diego Puschini, Lionel Torres, Fabien Clermidy, Gilles Sassatelli:
Dynamic Energy Optimization in Network-on-Chip-Based System-on-Chips. 564-577 - Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
Statistical Moment Estimation of Delay and Power in Circuit Simulation. 578-587 - Sergio Gómez, Francesc Moll
Lithography Aware Regular Cell Design Based on a Predictive Technology Model. 588-600 - Nabila Moubdi, Philippe Maurine, Robin Wilson, Sylvain Engels, Nadine Azémard, Vincent Dumettier, Pierre Busson:
On-Chip Process Variability Monitoring Flow. 601-606 - Nikolaos Andrikos, Luciano Lavagno, Fabio Campi, Davide Pandini:
Improving Electro-Magnetic Interference of Embedded Systems Through Jittered-Delay Desynchronization. 607-615
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