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Integration, Volume 72
Volume 72, May 2020
- Johanna Baehr
, Alessandro Bernardini, Georg Sigl, Ulf Schlichtmann
Machine learning and structural characteristics for reverse engineering. 1-12
- Pablo Saraza-Canflanca, Javier Diaz-Fortuny
A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level. 13-20 - Michele Caselli
Modeling and design of 3-D MPPT for ultra low power RF energy harvesters. 21-28 - Saleha Bano, Ghous Bakhsh Narejo, Syed M. Usman Ali
Flipped voltage follower based fourth order filter and its application to portable ECG acquisition system. 29-38 - M. Tanjidur Rahman
Defense-in-depth: A recipe for logic locking to prevail. 39-57 - Amir Najafi
Misalignment-aware energy modeling of narrow buses for data encoding schemes. 58-65 - Wenfa Zhan, Zhiwei Shao
Test patterns reordering method based on Gamma distribution. 66-71 - Feiran Liu, Chien-In Henry Chen:
High two-signal dynamic range and accurate frequency measurement for close frequency separation wideband digital receiver using adaptive gain control and adaptive thresholding. 72-81 - Lin Jiang, Yang Liu, Rui Shan, Yani Feng, Yuan Zhang, Xiaoyan Xie:
RDMM: Runtime dynamic migration mechanism of distributed cache for reconfigurable array processor. 82-91 - Anugrah Jain
TRACK: An algorithm for fault-tolerant, dynamic and scalable 2D mesh network-on-chip routing reconfiguration. 92-110 - Min Pan, Lili Pang, Jiaye Xie, Yufei Han, Qiqing Xu:
A 0.6V 44.6 ppm/ºC subthreshold CMOS voltage reference with wide temperature range and inherent leakage compensation. 111-122 - Maoyuan Qin, Xinmu Wang, Baolei Mao, Dejun Mu, Wei Hu:
A formal model for proving hardware timing properties and identifying timing channels. 123-133 - Navid Khoshavi, Mohammad Maghsoudloo
A survey on attack vectors in stack cache memory. 134-147 - Jani Babu Shaik
Analysis of SRAM metrics for data dependent BTI degradation and process variability. 148-162 - Mohamed F. Tolba, Ahmed S. Elwakil, Hammam Orabi, Mohammed Elnawawy
FPGA implementation of a chaotic oscillator with odd/even symmetry and its application. 163-170 - Libao Deng, Ning Sun, Ning Fu:
Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs. 171-182 - Reza Narimani, Bardia Safaei
A comprehensive analysis on the resilience of adiabatic logic families against transient faults. 183-193 - Alfio Di Mauro, Davide Rossi
Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI. 194-207
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