default search action
IEEE Transactions on Computers, Volume 29
Volume 29, Number 1, January 1980
- Tomlinson Gene Rauscher, Phillip M. Adams:
Microprogramming: A Tutorial and Survey of Recent Developments. 2-20 - Chris R. Jesshope:
The Implementation of Fast Radix 2 Transforms on Array Processors. 20-27 - Hanan Samet:
Efficient On-Line Proofs of Equalities and Inequalities of Formulas. 28-32 - Ayee Goundan, John P. Hayes:
Design of Totally Fault Locatable Combinational Networks. 33-44 - Shashi K. Mehra, Johnny W. Wong, Jayanti C. Majithia:
A Comparative Study of Some Two-Processor Organizations. 44-49
- Paul Cull:
Tours of Graphs, Digraphs, and Sequential Machines. 50-54 - Kolar L. Kodandapani, Dhiraj K. Pradhan:
Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets. 55-59 - R. M. M. Oberman:
Comments on "Modular Replacement of Combinational Switching Networks". 59-61
Volume 29, Number 2, February 1980
- Gene L. Haviland, Al A. Tuszynski:
A CORDIC Arithmethic Processor Chip. 68-79 - Michel C. Rahier, Paul G. A. Jespers:
Dedicated LSI for a Microprocessor-Controlled Hand-Carried OCR System. 79-88 - Yuzo Kita, Noboru Yamaguchi, Mamoru Sugie, Shigeru Yoshizawa:
The Development of a Bubble Memory Controller for Low-Cost File Use. 89-96 - Matt Townsend, Marcian E. Hoff Jr., Robert E. Holm:
An NMOS Microprocessor for Analog Signal Processing. 97-102 - Tsuneo Funabashi, Katsuaki Takagi, Toshiro Tsukada, Hideo Nakamura, Michio Hara:
An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital Converter. 102-107 - David A. Patterson, Carlo H. Séquin:
Design Considerations for Single-Chip Computers of the Future. 108-116 - Alan J. Weissberger:
An LSI Implementation of an Intelligent CRC Computer and Programmable Character Comparator. 116-124 - Rodger A. Cliff:
Acceptable Testing of VLSI Components Which Contain Error Correctors. 126-134 - Jan V. Zeman, H. Troy Nagle Jr.
:
A High-Speed Microprogrammable Digital Signal Processor Employing Distributed Arithmetic. 134-144 - Ayakannu Mathialagan, Nripendra N. Biswas:
Optimal Interconnections in the Design of Microprocessors and Digital Systems. 145-149 - Jega A. Arulpragasam, Robert A. Giggi, Richard F. Lary, Daniel T. Sullivan, Chin-Chang Wu:
Modular Minicomputers Using Microprocessors. 149-160 - John J. Lenahan, Fergus K. Fung:
Performance of Cooperative Loosely Coupled Microprocessor Architectures in an Interactive Data Base Task. 161-180 - Daniel Tabak, G. Jack Lipovski:
MOVE Architecture in Digital Controllers. 180-190
- K. Wayne Current:
High Density Integrated Computing Circuitry with Multiple Valued Logic. 191-195 - Robert J. Inkol, Savvas G. Chamberlain:
Design and Realization of a Two-Level 64K Byte CCD Memory System for Microcomputer Applications. 195-199 - Rodger A. Cliff:
Digital Multiplexing of Analog Data in a Microprocessor Controlled Data Acquisition System. 200-206 - James F. Burnell, Stephen C. Crist, Mohammed Arozullah:
Microprocessor Utilization in Satellite-Born Packet Switching. 206-208 - M. J. Ellis, G. R. Hovey, T. E. Stapinski:
MTEC: A Microprocessor System for Astronomical Telescope and Instrument Control. 208-211
Volume 29, Number 3, March 1980
- Douglas Stott Parker Jr.:
Notes on Shuffel/Exchange-Type Switching Networks. 213-222 - Melvin A. Breuer, Arthur D. Friedman:
Functional Level Primitives in Test Generation. 223-235 - Jean Davies Lesser, John J. Shedletsky:
An Experimental Delay Test Generator for LSI Logic. 235-248
- John P. Hayes:
Testing Memories for Single-Cell Pattern-Sensitive Faults. 249-254 - Stephen Y. H. Su, Edgar DuCasse:
A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures. 254-258 - Everett L. Johnson:
A Digital Quarter Square Multiplier. 258-261 - Israel Koren, Eitan Sadeh:
A New Approach to the Evaluation of the Reliability of Digital Systems. 261-267
Volume 29, Number 4, April 1980
- Meghanad D. Wagh, H. Ganesh:
A New Algorithm for the Discrete Cosine Transform of Arbitrary Number of Points. 269-277 - Anthony P. Reeves:
A Systematically Designed Binary Array Processor. 278-287 - Vinod K. Agarwal, Gerald M. Masson:
Generic Fault Characterizations for Table Look-Up Coverage Bounding. 288-299 - Jesse H. Jenkins, James A. Howard:
Control Overhead - A Performance Metric for Evaluating Control-Unit Designs. 300-308 - John L. Bruno, John W. Jones III, Kimming So:
Deterministic Scheduling with Pipelined Processors. 308-316 - Hideo Kitajima:
A Symmetric Cosine Transform. 317-323
- Ronald V. Book, Sai Choi Kwan:
On Uniquely Decipherable Codes with Two Codewords. 324-325 - R. W. Holgate, Roland N. Ibbett:
An Analysis of Instruction-Fetching Strategies in Pipelined Computers. 325-329 - V. E. Vickers, J. Silverman:
A Technique for Generating Specialized Gray Codes. 329-331 - David Paul Maher:
On Fourier Transforms Over Extensions of Finite Rings. 331-333 - P. S. Kamat:
Comments on "Algorithm for Fast Evaluation of Time Functions". 333
Volume 29, Number 5, May 1980
- Mark R. Brown, David P. Dobkin:
An Improved Lower Bound on Polynomial Multiplication. 337-340 - Earl E. Swartzlander Jr., Barry K. Gilbert:
Arithmetic for Ultra-High-Speed Tomography. 341-353 - Yehuda Wallach, Victor Konrad:
On Block-Parallel Methods for Solving Linear Equations. 354-359 - Raphael A. Finkel, Marvin H. Solomon:
Processor Interconnection Strategies. 360-371 - Chin-Hwa Lee:
Queueing Analysis of Global Locking Synchronization Schemes for Multicopy Databases. 371-384 - Hossein Jafari, Ted G. Lewis, John D. Spragins:
Simulation of a Class of Ring-Structured Networks. 385-392
- Daniel Gajski:
Parallel Compressors. 393-398 - William W. Warlick Jr., John E. Hershey:
High-Speed M-Sequence Generators. 398-400 - K. Wayne Current:
Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders. 400-403 - K. Wayne Current:
A High Data-Rate Digital Output Correlator Design. 403-405 - Takeomi Tamesada:
Sequential Machines Having Quasi-Stable States. 405-408 - Dennis R. Morgan:
Autocorrelation Function of Sequential M-Bit Words Taken from an N-Bit Shift Register (PN) Sequence. 408-410 - Jacob Savir:
Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection. 410-416
Volume 29, Number 6, June 1980
- Dong S. Suk, Sudhakar M. Reddy:
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories. 419-429 - Satish M. Thatte, Jacob A. Abraham:
Test Generation for Microprocessors. 429-441 - Jacob Savir:
Syndrome-Testable Design of Combinational Circuits. 442-451 - Miron Abramovici, Melvin A. Breuer:
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis. 451-460 - Sivanarayana Mallela, Gerald M. Masson:
Diagnosis Without Repair for Hybrid Fault Situations. 461-470 - Dhiraj K. Pradhan:
A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications. 471-481 - Bengt E. Ossfeldt, Ingmar Jonsson:
Recovery and Diagnostics in the Central Control of the AXE Switching System. 482-491 - Richard M. Sedmak, Harris L. Liebergot:
Fault Tolerance of a General Purpose Computer Implemented by Very Large Scale Integration. 492-500 - John F. Meyer, David G. Furchtgott, Liang T. Wu:
Performability Evaluation of the SIFT Computer. 501-509
- James E. Smith:
Measures of the Effectiveness of Fault Signature Analysis. 510-514 - René David, Pascale Thévenod-Fosse:
Minimal Detecting Transition Sequences: Application to Random Testing. 514-518 - Vinod K. Agarwal:
Multiple Fault Detection in Programmable Logic Arrays. 518-522 - Mark G. Karpovsky, Stephen Y. H. Su:
Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines. 523-527 - J. Galiay, Yves Crouzet, M. Vergniault:
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability. 527-531 - Yves Crouzet, Christian Landrault:
Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor. 532-537 - Daniel Etiemble:
Multivalued I2L Circuits for TSC Checkers. 537-540 - Luca Simoncini, F. Saheban, Arthur D. Friedman:
Design of Self-Diagnosable Multiprocessor Systems with Concurrent Computation and Diagnosis. 540-546 - P. A. Lee, N. Ghani, K. Heron:
A Recovery Cache for the PDP-11. 546-549
Volume 29, Number 7, July 1980
- Kin-Man Chung, Fabrizio Luccio, C. K. Wong:
On the Complexity of Sorting in Magnetic Bubble Memory Systems. 553-563 - Frances L. Van Scoy:
The Parallel Recognition of Classes of Graphs. 563-570 - Jon Louis Bentley, Derick Wood:
An Optimal Worst Case Algorithm for Reporting Intersections of Rectangles. 571-577 - Hiroshi Hagiwara, Shinji Tomita, Shigeru Oyanagi, Kiyoshi Shibayama:
A Dynamically Microprogammable Computer with Low-Level Parallelism. 577-595 - Simon S. Lam:
Packet Broadcast Networks - A Performance Analysis of the R-ALOHA Protocol. 596-603 - Tich T. Dao, Marc Davio, Colette Gossart:
Complex Number Arithmetic with Odd-Valued Logic. 604-611 - Samuel T. Chanson, Prem S. Sinha:
Optimization of Memory Hierarchies in Multiprogrammed Computer Systems With Fixed Cost Constraint. 611-618 - Francis Y. L. Chin, K. Samson Fok:
Fast Sorting Algorithms on Uniform Ladders (Multiple Shift-Register Loops). 618-631 - Omar Wing, John W. Huang:
A Computation Model of Parallel Solution of Linear Equations. 632-638 - Bulent I. Dervisoglu, Howard A. Sholl:
Theory and Design of Mixed-Mode Sequential Machines. 639-648 - John C. Sutton, Jon G. Bredeson:
Minimal Redundant Logic for High Reliability and Irredundant Testability. 648-656
- William A. Porter:
Polylogic Realization of Switching Functions. 657-659 - Chris R. Jesshope:
Some Results Concerning Data Routing in Array Processors. 659-662 - Moiez A. Tapia, Jerry H. Tucker:
Complete Solution of Boolean Equations. 662-665 - Bella Bose, T. R. N. Rao:
Separating and Completely Separating Systems and Linear Codes. 665-668 - René David:
Testing by Feedback Shift Register. 668-673 - Jacob Savir:
Detection of Single Intermittent Faults in Sequential Circuits. 673-678
Volume 29, Number 8, August 1980
- Ikuo Nishioka, Takuji Kurimoto, Seiji Yamamoto, Toru Chiba, Isao Shirakawa, Hiroshi Ozaki:
An Approach to Gate Assignment and Module Placement for Printed Wiring Boards. 681-688 - Sheldon S. L. Chang:
Multiple-Read Single-Write Memory and Its Applications. 689-694 - Chuan-lin Wu, Tse-Yun Feng:
On a Class of Multistage Interconnection Networks. 694-702 - Jan Weglarz
Multiprocessor Scheduling with Memory Allocation - A Deterministic Approach. 703-709 - George P. Engelberg, James A. Howard, Duncan A. Mellichamp:
Job Scheduling in a Single-Node Hierarchical Network for Process Control. 710-719 - John F. Meyer:
On Evaluating the Performability of Degradable Computing Systems. 720-731
- Masaru Yamamoto:
A Method for Minimizing Incompletely Specified Sequential Machines. 732-736 - Janak H. Patel:
An Alternative to the Distributed Pipeline. 736-737 - Peter Klein, Mike Paterson:
Asymtotically Optimal Circuit for a Storage Access Function. 737-738 - Richard W. Heuft, Warren D. Little:
Convolution Computer. 738-740 - C. K. Yuen:
Negabinary A/D Conversion. 740-741 - Karl E. Stoffers:
Test Sets for Combinational Logic - The Edge-Tracing Approach. 741-746 - Edward W. Page:
Minimally Testable Reed-Muller Canonical Forms. 746-750 - Jon C. Muzio:
Composite Spectra and the Analysis of Switching Circuits. 750-753 - Norman M. Martin, Stephen P. Hufnagel:
Conditional-Sum Early Completion Adder Logic. 753-756 - Yakov I. Fet:
Comments on "A Design of a Fast Cellular Associative Memory for Ordered Retrieval". 756-757 - Wolfgang Coy:
A Remark on the Nonminimality of Certain Multiple Fault Detection Algorithms. 757-759
Volume 29, Number 9, September 1980
- David A. Padua, David J. Kuck, Duncan H. Lawrie:
High-Speed Multiprocessors and Compilation Techniques. 763-776 - Dhiraj K. Pradhan, Kolar L. Kodandapani:
A Uniform Representation of Single- and Multistage Interconnection Networks Used in SIMD Machines. 777-791 - Howard Jay Siegel:
The Theory Underlying the Partitioning of Permutation Networks. 791-801 - Chuan-lin Wu, Tse-Yun Feng:
The Reverse-Exchange Interconnection Network. 801-811 - Carla Schlatter Ellis:
Concurrent Search and Insertion in AVL Trees. 811-817 - Ossama Ibrahim El-Dessouki, Wing H. Huen:
Distributed Enumaration on Between Computers. 818-825
- Stephen J. Allan, Arthur E. Oldehoeft:
A Flow Analysis Procedure for the Translation of High-Level Languages to a Data Flow Language. 826-831 - Kai Hwang, Lionel M. Ni:
Resource Optimization of a Parallel Computer for Multiple Vector Processing. 831-836 - Kenneth E. Batcher:
Design of a Massively Parallel Processor. 837-840 - Anthony P. Reeves, John D. Bruner:
Efficient Function Implementation for Bit-Serial Parallel. 841-844
Volume 29, Number 10, October 1980
- King-sun Fu:
Recent Developments in Pattern Recognition. 845-854 - Gian Carlo Bongiovanni, Fabrizio Luccio:
Maintaining Sorted Files in a Magnetic Bubble Memory. 855-863 - Kin-Man Chung, Fabrizio Luccio, C. K. Wong:
A Tree Storage Scheme for Magnetic Bubble Memories. 864-874 - Robert B. Tilove:
Set Membership Classification: A Unified Approach to Geometric Intersection Problems. 874-883 - Pierre G. Jansen, Joep L. W. Kessels:
The DIMOND: A Component for the Modular Construction of Switching Networks. 884-889 - Anthony S. Wojcik, Kwang-Ya Fang:
On the Design of Three-Valued Asynchronous Modules. 889-898 - Graham A. Jullien:
Implementation of Multiplication, Modulo a Prime Number, with Applications to Number Theoretic Transforms. 899-905 - Kim P. Gostelow, Robert E. Thomas:
Performance of a Simulated Dataflow Computer. 905-919
- Steven E. Elkind, Daniel P. Siewiorek:
Reliability and Performance of Error-Correcting Memory and Register Arrays. 920-927 - Grazia Lotti, Francesco Romani
Application of Approximating Algorithms to Boolean Matrix Multiplication. 927-928 - Hussein T. Mouftah, Kenneth C. Smith, Zvonko G. Vranesic:
Ternary Rate-Multipliers. 929-931 - Marc Davio:
Read-Only Memory Implementation of Discrete Function. 931-934 - Udi Manber:
System Diagnosis with Repair. 934-937 - James R. Armstrong:
The Complexity of Computational Circuits Versus Radix. 937-941 - Luigi Dadda:
Composite Parallel Counters. 942-946 - Earl E. Swartzlander Jr.:
Merged Arithmetic. 946-950 - Sany Leinwand, T. Lamdan:
Dynamic Boolean Algebras. 950-953 - John W. Stoughton:
Modification of "A Least Mean Squares CUBIC Algorithm for On-Line Differential of Sampled Analog Signals". 953
Volume 29, Number 11, November 1980
- Keith L. Doty, Joel D. Greenblatt, Stanley Y. W. Su:
Magnetic Bubble Memory Architectures for Supporting Associative Searching of Relational Databases. 957-970 - Wesley W. Chu, Michael Yih-Chung Shen:
Hierarchical Routing and Flow Control Policy (HRFC) for Packet Switched Networks. 971-977 - Ayee Goundan, John P. Hayes:
Identification of Equivalent Faults in Logic Networks. 978-985 - Abraham Kandel, Joan M. Francioni:
On the Properties and Applications of Fuzzy-Valued Switching Functions. 986-994 - N. K. Samari, G. Michael Schneider:
A Queueing Theory-Based Analytic Model of a Distributed Computer Network. 994-1001 - Ying W. Ng, Algirdas Avizienis:
A Unified Reliability Model for Ault-Tolerant Computers. 1002-1011
- Stephen C. Crist:
Synthesis of Combinational Logic Using Decomposition and Probability. 1013-1016 - J. M. Glass:
An Efficient Method for Improving Reliability of a Pipeline FFT. 1017-1020 - Kewal K. Saluja:
Synchronous Sequential Machines: A Modular and Testable Design. 1020-1025 - Sumit Dasgupta, Carlos R. P. Hartmann, Luther D. Rudolph:
Dual-Mode Logic for Function-Independent Fault Testing. 1025-1029 - K. M. Chung, C. K. Wong:
Construction of a Generalized Connector with 5.8 n log2 n Edges. 1029-1032 - Dharma P. Agrawal:
On Negabinary-Binary Arithmetic Relationships an Their Hardware Reciprocity. 1032-1035
Volume 29, Number 12, December 1980
- Rami R. Razouk, Gerald Estrin:
Modeling and Verification of Communication Protocols in SARA: The X.21 Interface. 1038-1052 - Parviz Kermani, Leonard Kleinrock:
A Tradeoff Study of Switching Systems in Computer Communication Networks. 1052-1060 - Georges Gardarin, Wesley W. Chu:
A Distributed Control Algorithm for Reliably and Consistently Updating Replicated Databases. 1060-1068 - Peter P. Chen, Jacky Akoka:
Optimal Design of Distributed Information Systems. 1068-1080 - Michael J. Flynn, John L. Hennessy:
Parallelism and Representation Problems in Distributed Systems. 1060-1086 - Mario J. Gonzalez Jr., Bernard W. Jordan Jr.:
A Framework for the Quantitative Evaluation of Distributed Computer Systems. 1087-1094 - James R. McGraw:
Data Flow Computing - Software Development. 1095-1103 - Reid G. Smith:
The Contract Net Protocol: High-Level Communication and Control in a Distributed Problem Solver. 1104-1113 - Steven I. Kartashev, Svetlana P. Kartashev:
Problems of Designing Supersystems with Dynamic Architectures. 1114-1132 - Larry D. Wittie, André M. Van Tilborg:
MICROS, A Distributed Operating System for MICRONET, A Reconfigurable Network Computer. 1133-1144 - Victor R. Lesser, Lee D. Erman:
Distributed Interpretation: A Model and Experiment. 1144-1163
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-01 00:01 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: