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ACM Transactions on Architecture and Code Optimization, Volume 21
Volume 21, Number 1, March 2024
- Longfei Luo
, Dingcui Yu
Critical Data Backup with Hybrid Flash-Based Consumer Devices. 1:1-1:23 - Peng Chen
DAG-Order: An Order-Based Dynamic DAG Scheduling for Real-Time Networks-on-Chip. 2:1-2:24 - Zhang Jiang
JiuJITsu: Removing Gadgets with Safe Register Allocation for JIT Code Generation. 3:1-3:26 - Hayfa Tayeb
Autovesk: Automatic Vectorized Code Generation from Unstructured Static Kernels Using Graph Transformations. 4:1-4:25 - Xueying Wang
Fast Convolution Meets Low Precision: Exploring Efficient Quantized Winograd Convolution on Modern CPUs. 5:1-5:26 - Hao Fan, Yiliang Ye
QoS-pro: A QoS-enhanced Transaction Processing Framework for Shared SSDs. 6:1-6:25 - Yunping Zhao
SAC: An Ultra-Efficient Spin-based Architecture for Compressed DNNs. 7:1-7:26 - Tong-Yu Liu
Efficient Cross-platform Multiplexing of Hardware Performance Counters via Adaptive Grouping. 8:1-8:26 - Lei Liu
QuCloud+: A Holistic Qubit Mapping Scheme for Single/Multi-programming on 2D/3D NISQ Quantum Computers. 9:1-9:27 - Lingxi Wu
Abakus: Accelerating k-mer Counting with Storage Technology. 10:1-10:26 - Seokwon Kang
ISP Agent: A Generalized In-storage-processing Workload Offloading Framework by Providing Multiple Optimization Opportunities. 11:1-11:24 - Prasoon Mishra
COWS for High Performance: Cost Aware Work Stealing for Irregular Parallel Loop. 12:1-12:26 - Joongun Park
Hardware-hardened Sandbox Enclaves for Trusted Serverless Computing. 13:1-13:25 - Tyler N. Allen
Fine-grain Quantitative Analysis of Demand Paging in Unified Virtual Memory. 14:1-14:24 - Zhonghua Wang
Rcmp: Reconstructing RDMA-Based Memory Disaggregation via CXL. 15:1-15:26 - Linbo Long
WA-Zone: Wear-Aware Zone Management Optimization for LSM-Tree on ZNS SSDs. 16:1-16:23 - Zhihua Fan
Improving Utilization of Dataflow Unit for Multi-Batch Processing. 17:1-17:26 - Dunbo Zhang
Extension VM: Interleaved Data Layout in Vector Memory. 18:1-18:23 - Can Firtina
ApHMM: Accelerating Profile Hidden Markov Models for Fast and Energy-efficient Genome Analysis. 19:1-19:29 - Khalid Ahmad
Exploring Data Layout for Sparse Tensor Times Dense Matrix on GPUs. 20:1-20:20
Volume 21, Number 2, June 2024
- Chandra Sekhar Mummidi
Highly Efficient Self-checking Matrix Multiplication on Tiled AMX Accelerators. 21 - Zhonghua Wang
WIPE: A Write-Optimized Learned Index for Persistent Memory. 22 - Gino A. Chacon
Coherence Attacks and Countermeasures in Interposer-based Chiplet Systems. 23 - Yan Wei
A Concise Concurrent B+-Tree for Persistent Memory. 24 - Fareed Qararyah
An Efficient Hybrid Deep Learning Accelerator for Compact and Heterogeneous CNNs. 25 - Fernando Fernandes dos Santos
Assessing the Impact of Compiler Optimizations on GPUs Reliability. 26 - Valentin Isaac-Chassande
Dedicated Hardware Accelerators for Processing of Sparse Matrices and Vectors: A Survey. 27 - Benyi Xie
An Instruction Inflation Analyzing Framework for Dynamic Binary Translators. 28 - Samuel Rac
Cost-aware Service Placement and Scheduling in the Edge-Cloud Continuum. 29 - Feng Xue
Tyche: An Efficient and General Prefetcher for Indirect Memory Accesses. 30 - Kunpeng Xie
Winols: A Large-Tiling Sparse Winograd CNN Accelerator on FPGAs. 31 - Ke Liu
SLAP: Segmented Reuse-Time-Label Based Admission Policy for Content Delivery Network Caching. 32 - Panagiotis Miliadis
Architectural Support for Sharing, Isolating and Virtualizing FPGA Resources. 33 - Haitao Du
FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration. 34 - Michael Canesche
The Droplet Search Algorithm for Kernel Scheduling. 35 - Asmita Pal
Camouflage: Utility-Aware Obfuscation for Accurate Simulation of Sensitive Program Traces. 36 - Chengying Huan
TEA+: A Novel Temporal Graph Random Walk Engine with Hybrid Storage Architecture. 37 - Soojin Hwang
Cerberus: Triple Mode Acceleration of Sparse Matrix and Vector Multiplication. 38 - Siddhartha Raman Sundara Raman
NEM-GNN: DAC/ADC-less, Scalable, Reconfigurable, Graph and Sparsity-Aware Near-Memory Accelerator for Graph Neural Networks. 39 - Yan Chen
xMeta: SSD-HDD-hybrid Optimization for Metadata Maintenance of Cloud-scale Object Storage. 40 - Vidush Singhal
Orchard: Heterogeneous Parallelism and Fine-grained Fusion for Complex Tree Traversals. 41
Volume 21, Number 3, September 2024
- Hajar Falahati
Cross-core Data Sharing for Energy-efficient GPUs. 42:1-42:32 - Ching-Jui Lee
ReSA: Reconfigurable Systolic Array for Multiple Tiny DNN Tensors. 43:1-43:24 - Ziheng Wang
An Example of Parallel Merkle Tree Traversal: Post-Quantum Leighton-Micali Signature on the GPU. 44:1-44:25 - Jiang Wu
Knowledge-Augmented Mutation-Based Bug Localization for Hardware Design Code. 45:1-45:26 - Chen Ding
D2Comp: Efficient Offload of LSM-tree Compaction with Data Processing Units on Disaggregated Storage. 46:1-46:22 - Zhuohao Wang
iSwap: A New Memory Page Swap Mechanism for Reducing Ineffective I/O Operations in Cloud Environments. 47:1-47:24 - Junkaixuan Li
GraphSER: Distance-Aware Stream-Based Edge Repartition for Many-Core Systems. 48:1-48:25 - Ke Wu
COER: A Network Interface Offloading Architecture for RDMA and Congestion Control Protocol Codesign. 49:1-49:26 - Qunyou Liu
Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads. 50:1-50:23 - Dongmoon Min
CoolDC: A Cost-Effective Immersion-Cooled Datacenter with Workload-Aware Temperature Scaling. 51:1-51:27 - Hai Zhou
Stripe-schedule Aware Repair in Erasure-coded Clusters with Heterogeneous Star Networks. 52:1-52:24 - Bobin Deng
Fixed-point Encoding and Architecture Exploration for Residue Number Systems. 53:1-53:27 - Yizhuo Wang
Optimization of Sparse Matrix Computation for Algebraic Multigrid on GPUs. 54:1-54:27 - Luming Wang
Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access. 55:1-55:28 - Yunping Zhao
SAL: Optimizing the Dataflow of Spin-based Architectures for Lightweight Neural Networks. 56:1-56:27 - Kai Lu
Scythe: A Low-latency RDMA-enabled Distributed Transaction System for Disaggregated Memory. 57:1-57:26 - Wangqi Peng
Lavender: An Efficient Resource Partitioning Framework for Large-Scale Job Colocation. 58:1-58:23 - Feng Zhang
Achieving Tunable Erasure Coding with Cluster-Aware Redundancy Transitioning. 59:1-59:24 - Ataberk Olgun
Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture. 60:1-60:29 - Xiaohui Wei
ReIPE: Recycling Idle PEs in CNN Accelerator for Vulnerable Filters Soft-Error Detection. 61:1-61:26 - Qiao Li
Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories. 62:1-62:26 - Jiahong Xu
ReHarvest: An ADC Resource-Harvesting Crossbar Architecture for ReRAM-Based DNN Accelerators. 63:1-63:26 - Jiang Wu
Time-Aware Spectrum-Based Bug Localization for Hardware Design Code with Data Purification. 64:1-64:25
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