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35th VLSI Design 2022: Bangalore, India
- 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, VLSID 2022, Bangalore, India, February 26 - March 2, 2022. IEEE 2022, ISBN 978-1-6654-8505-0
- Shraman Mukherjee, Sumantra Seth, Saurabh Saxena:
A 5-Gb/s PAM4 Voltage Mode Transmitter with Current Mode Continuous Time Linear Equalizer. 1-5 - Javed S. Gaggatur, Miryala Chandra Shekar, Komal Deshmukh:
A 0.009mm2, 0-230mA Wide-range Load Current Output Capacitor-less Low Dropout Regulator for High Bandwidth Memory parallel IOs. 6-10 - Jayaraj U. Kidav, Akula Sri Rama Pavan, M. Rajesh, Navin Kumar:
A PC based Ultrasound back-end signal processor using Intel® Performance Primitives. 11-15 - Kalyan Baital
, Amlan Chakrabarti, Biswadeep Chatterjee, Stefan Holst, Xiaoqing Wen:
Power and Energy Safe Real-Time Multi-Core Task Scheduling. 16-21 - Aditi Singh:
Equivalence Checking of Non-Binary Combinational Netlists. 22-27 - Jitendra Kumar, Asutosh Srivastava:
Dynamic Variable Ordering during Algebraic Backward Rewriting for Formal Verification of Multipliers. 28-32 - Arpan Jain, Abhishek Pullela, Ashfakh Ali, Zia Abbas:
A 180o Phase Shift Biasing Technique for Realizing High PSRR in Low Power Temperature Sensors. 33-38 - Ankur Bal, Sharad Gupta, Rupesh Singh:
A Real Time Multi-Bit DAC Mismatch Estimation & Correction Technique For Wideband Continuous Time Sigma Delta Modulators. 39-43 - Santunu Sarangi, Indranil Som, T. K. Bhattacharyya:
A 10 Gb/s On-chip Jitter Measurement Circuit Based on Transition Region Scanning Method. 44-49 - Y. Pawan Kumar Gururaj, Sai Anirudh Karre, Raghav Mittal, Y. Raghu Reddy, Syed Azeemuddin:
Customizable Head-mounted Device for Detection of Eye Disorders using Virtual Reality. 50-55 - Sachin Ramesh Pundkar, Surajit Pradeep Karmakar, Samir Kumar Mishra, Surendra Singh, Tushar Vrind:
Energy Aware Dynamic Load Balancer for Embedded Multi-core Systems. 56-61 - Niraj Kumar, Arijit Mondal:
Energy Optimized Non-preemptive Scheduling of Real-Time Tasks with Precedence and Reliability Constraints. 62-67 - Santanu Kundu, Manoranjan Prasad, Sashank Nishad, Sandeep Nachireddy, Harikrishnan K:
MLIR: Machine Learning based IR Drop Prediction on ECO Revised Design for Faster Convergence. 68-73 - Anjali Agrawal, Smruti R. Sarangi:
NanoLeak: A Fast Analytical Green's Function-based Leakage-aware Thermal Simulator. 74-79 - Rushabh Shah, Krishna Agrawal, G. Anjaneyulu, Vishnu Bhaskari:
Automated Debugger for Optimum Physical Clock Structure Targeting Minimal Latency. 80-85 - M. K. Aparna Nair, Police Manoj Kumar Reddy, Y. L. Abijith, Venkatesh Rajagopalan, Soumya J.
Hardware Implementation of Network Interface Architecture for RISC-V based NoC-MPSoC Framework. 86-91 - Sri Harsha Gade, Mitali Sinha, Madhur Kumar, Sujay Deb:
Scalable Hybrid Cache Coherence Using Emerging Links for Chiplet Architectures. 92-97 - Sunil Kumar C. R, Aruna Kumar, Sanjib Basu:
Novel Circuit Architecture for configurable eDP and MIPI DPHY IO. 98-101 - M. R. Ashuthosh, Santosh Krishna, Vishvas Sudarshan, Srinivasan Subramaniyan, Madhura Purnaprajna:
MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication. 102-107 - Mohammad Ebrahimabadi, Mohamed F. Younis, Wassila Lalouani, Naghmeh Karimi:
An Attack Resilient PUF-based Authentication Mechanism for Distributed Systems. 108-113 - Akshara Ravi
Static Malware Analysis using ELF features for Linux based IoT devices. 114-119 - Asmit De, Swaroop Ghosh:
HeapSafe: Securing Unprotected Heaps in RISC-V. 120-125 - Abdulrahman Alaql, Aritra Dasgupta, Md. Moshiur Rahman, Swarup Bhunia
SEVA: Structural Analysis based Security Evaluation of Sequential Locking. 126-131 - Ayan Chakraborty
Tracking Coverage Artefacts for Periodic Signals using Sequence-based Abstractions. 132-137 - Kritanta Saha, Sudipta Paul, Pritha Banerjee
Stitch-avoiding Global Routing for Multiple E-Beam Lithography. 138-143 - Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia
Robust Estimation of FPGA Resources and Performance from CNN Models. 144-149 - Ankit Gupta, Adrita Barari, Damini, Keerthi Kiran Jagannathachar, Seungwoo Lee, Janghoon Oh, Jungha Kim, Min-Joo Kim:
Identifying Combination of Defects and Unknown Defects on Semiconductor Wafers using Deep Learning and Hierarchical Reclustering. 150-155 - Sumanta Pyne:
An Architectural support for Digital Microfluidic based Hot-Spot free Computing. 156-161 - Dola Ram, Suraj Panwar, Kuruvilla Varghese:
Hardware Accelerator for Capsule Network based Reinforcement Learning. 162-167 - Bodepu Sai Tirumala Naidu
SCENIC: An Area and Energy-Efficient CNN-based Hardware Accelerator for Discernable Classification of Brain Pathologies using MRI. 168-173 - Neelam Surana, Pramod Kumar Bharti, Bachu Varun Tej, Joycee Mekie:
Mixed-8T: Energy-Efficient Configurable Mixed-VT SRAM Design Techniques for Neural Networks. 174-179 - Michalis Piponidis
Towards a Fully Autonomous UAV Controller for Moving Platform Detection and Landing. 180-185 - Adithya Sunil Edakkadan
A 2.75-2.94 GHz Voltage Controlled Oscillator with Low Gain Variation for Quantum Sensing Applications. 186-191 - Abhishek Srivastava, Baibhab Chatterjee
A Low Phase Noise 30 GHz Oscillator Topology for Resonant-Fin-Transistors Based High-Q On-chip Resonators in 14 nm Technology. 192-197 - Ashish Papreja, Sresthavadhani Mantha, Abhishek Srivastava:
Design Methodology of Low Phase Noise mmWave Oscillator with Partial Cancellation of Static Capacitance of High-Q On-chip MEMS Resonator. 198-203 - K. Vinay, Vikas Vazhayil, Madhav Rao:
An event driven approximate bio-electrical model generating surface electromyography RMS features. 204-209 - S. Raghuram, N. Shashank:
Approximate Adders for Deep Neural Network Accelerators. 210-215 - Kedar Janardan Dhori, Promod Kumar, Christophe Lecocq, Pascal Urard, Olivier Callen, Florian Cacho, Maryline Parra, Prashant Pandey, Daniel Noblet:
40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode. 216-221 - Vaibhavi Solanki, Rahul Ranjan Kumar, Praveen Ghagare, Anand D. Darji:
Low Power and Area Efficient Approximate 2D-DCT Architecture for Wireless Capsule Endoscopy. 222-227 - Chandan Kumar, Rahul Kumar, Anuj Grover, Shouri Chatterjee, Kedar Janardan Dhori, Harsh Rawat:
Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI. 228-233 - Krishnendu Guha, Amlan Chakrabarti:
Criticality based Reliability from Rowhammer Attacks in Multi-User-Multi-FPGA Platform. 234-239 - Rajath Vasudevamurthy:
Pulse-width Modulation Technique for Generation of Multiple Analog Voltages for On-chip Calibration. 240-245 - Habibur Rahaman, Santanu Chattopadhyay
Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking. 246-251 - Srinivasa Prasad Soundararajan, Harry Gee, Adam Whitworth:
Parasitic Interactions with Intermediate Substrates and Methods to Mitigate their Impact: A Case Study in Voltage Protection ICs. 252-256 - Anupama Deo, Ashis Maity
A High Voltage Level Shifter for Automotive Buck Converter with a Fast Transient Response. 257-262 - V. Naveen Chander, Kuruvilla Varghese:
A Soft RISC-V Vector Processor for Edge-AI. 263-268 - Kattekola Naresh, Y. Padma Sai
Design of 8-bit Dadda Multiplier using Gate Level Approximate 4: 2 Compressor. 269-274 - Mahabubul Alam, Swaroop Ghosh:
DeepQMLP: A Scalable Quantum-Classical Hybrid Deep Neural Network Architecture for Classification. 275-280 - Amina Haroon, Sneh Saurabh:
Image Completion using a Sparse Probabilistic Spin Logic Network. 281-286 - U. S. Shikha
Threshold Voltage Modeling of Negative Capacitance Double Gate TFET. 287-291 - Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta:
Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications. 292-296 - Mani Shankar Yadav, Avinash Kumar Gupta, Kanupriya Varshney, Brajesh Rawat:
How Good Silicon Oxide-based Memristor Can be? 297-302 - Akhilesh Rawat, Anjali Goel, Brajesh Rawat:
Role of Interface Trap Charges in the Performance of Monolayer and Bilayer MoS2-based Field-Effect Transistors. 303-308
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last updated on 2024-09-26 23:30 CEST by the dblp team
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