default search action
24th VDAT 2020: Bhubaneswar, India
- 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020. IEEE 2020, ISBN 978-1-7281-9369-4
- B. B. Shabarinath, P. Muralidhar:
Custom-IP for Gradient Descent Optimization based on Hardware/Software Co-design Paradigm. 1-6 - Abin Bassam Ayub, Pallab Kumar Nath, Venkat Rangan, Chetan Singh Thakur:
FPGA based Compressive Sensing Framework for Video Compression on Edge Devices. 1-5 - Dhirendra Kumar
, Chaitanya Dnyaneshwar Jadhav, Prasanna Kumar Misra, Manish Goswami:
Opto-Radio Noise based True Random Number Generator. 1-5 - Sahan Panguluru, Jai Gopal Pandey:
A Highly Stable and Robust 7T SRAM Cell using Memristor. 1-4 - Satya Sai Srinivas Nettimi
Digital Architecture for Instantaneous V/UV/S Classification of Noise Free Speech Segments. 1-6 - Spoorthi M. N.
A Decimal Multiplier With Improved Speed Using Semi-Parallel Iterative Approach. 1-6 - Surya Padma, Sounak Das, Subhajit Sen, Chetan D. Parikh
High Performance Operational Amplifier with 90dB Gain in SCL 180nm Technology. 1-5 - Jayanta Paul
Evaluation of Face Recognition Schemes for Low-computation IoT System Design. 1-6 - Karam Singh
Scalable VLSI Architecture for Hadamard Transforms of HEVC/H.265 Video Coding Standard. 1-5 - Amartya Dutta, Riya Majumder, Debasis Dhal, Rajat Kumar Pal:
A Novel Droplet Routing Algorithm with Behavioral Performances in Hexagonal Electrode based DMFB. 1-6 - Sree Ranjani Rajendran
KARNA for a Trustable Hardware. 1-4 - Anand Verma, Rutwik Pandit, Sushrut Thakur, Ameya Mungekar, Payal Shah, Surendra Singh Rathod
Modelling the Spiking Behaviour of Ganglion Cells. 1-6 - Akshay Birari, Piyush Birla, Kuruvilla Varghese, Bharadwaj S. Amrutur:
A RISC-V ISA Compatible Processor IP. 1-6 - Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler
Post Synthesis-Optimization of Reversible Circuit using Template Matching. 1-4 - Smrutilekha Samanta
A 10-bit 500 MSPS Segmented CS-DAC of > 77 dB SFDR upto the Nyquist with Hexa-decal biasing. 1-4 - Aishwarya Kagalkar, Raghuram S:
CORDIC Based Implementation of the Softmax Activation Function. 1-4 - Shabbir Darbar, J. Mervin, David Selvakumar:
Side Channel Leakage Assessment Strategy On Attack Resistant AES Architectures. 1-6 - Palakurthi Ravali, Purbasha Panda, Madhav Rao:
Design and Analysis of Ultra-Low Power Adiabatic Computational Subsystem Based on Symmetric Stacking. 1-6 - Shashank Neeraj Dwivedi, Ashish Kumar Seth, Anuj Grover
Design & Benchmark of Single Bit & Multi Bit Sequential Elements in 65nm for Low Standby Power Consumption. 1-6 - Pallab Pran Dutta, Arun Mohan B, Saroj Mondal:
An 18 mV Offset, 193 ps Sensing Delay, and Low Static Current Sense Amplifier for SRAM. 1-4 - Richa Sharma
A New Hardware Trojan Detection Technique using Class Weighted XGBoost Classifier. 1-6 - Anil Kumar Rajput, Manisha Pattanaik:
Energy Efficient 9T SRAM With R/W Margin Enhanced for beyond Von-Neumann Computation. 1-4 - Rajat Bhattacharjya
ReARM: A Reconfigurable Approximate Rounding-Based Multiplier for Image Processing. 1-4 - Sisir Kumar Jena
Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis. 1-6 - Gayatri Saripalli, Priyank H. Prajapati, Anand D. Darji:
CSD Optimized DWT Filter for ECG Denoising. 1-6 - Ankush Chunn, Akshay Agrawal, Alok Naugarhiya:
An 8T TG-DTMOS Based Subthreshold SRAM Cell with Improved Write Ability and Access Times. 1-6 - Nitanshu Chauhan, Govind Bajpai, Shashank Banchhor, Navjeet Bagga
Analysis of Transient Negative Capacitance Characteristics for Stabilization and Amplification. 1-5 - Subhadip Poria, Shelly Garg, Sneh Saurabh
Suppression of Ambipolar current in Tunnel Field-Effect Transistor using Field-Plate. 1-6 - Dinesh Rotake, Anand D. Darji, Jitendra Singh:
Ultrasensitive Multi-Arm-Microcantilever-Based Piezoresistive Sensor for BioMEMS Application. 1-6 - Rajul Bansal
PRESENT Crypto-core as Closely-coupled Coprocessor for Efficient Embedded SoCs. 1-6 - Onkar Choudhari, Marisha Chopade, Sourabh Chopde, Swarali Dabhadkar, Vaishali V. Ingale
HARDWARE ACCELERATOR: IMPLEMENTATION OF CNN ON FPGA FOR DIGIT RECOGNITION. 1-6 - Nilanjana Das, Joy Halder, Baisakhi Das, Biplab K. Sikdar:
Exploring Hard to Detect Sequential Hardware Trojans. 1-6 - Harsha M. V., B. P. Harish:
Artificial Neural Network Model for Design Optimization of 2-stage Op-amp. 1-5 - Jitumani Sarma, Shatadal Chatterjee, Rakesh Biswas
An Adaptive Digitally Tuned Flash-based LDO with Reduced Hardware for Sensor Nodes in WBAN. 1-6 - Jagadheesh Samala, Harshvardhan C. Takawale
Fault-Tolerant Routing Algorithm for Mesh based NoC using Reinforcement Learning. 1-6 - Soumya Sambit Rath, Debiprasad Priyabrata Acharya:
A Low Power Analog-to-Information Converter for Wireless Receivers. 1-6 - Aneek Jash, Ayut Ghosh
3D-NoCNN: NoC based Clustered Architecture for Neural Networks. 1-4 - Jai Shankar Kumar, Babli Kumari, Prashant Kumar, Ankita Verma, Pritesh Kumar Yadav
Design of Transceiver at 865-867 MHz Band using UMC 180 nm CMOS Technology. 1-5 - Kanika Monga, Lakshaya Maheshwari, Nitin Chaturvedi, S. Gurunarayanan:
Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array. 1-4 - Vaibhav Verma
Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology. 1-6 - Surbhi Chhabra
Design and Analysis of Secure One-way Functions for the Protection of Symmetric Key Cryptosystems. 1-6 - Mishal Kumar, Anuj Grover
A 0.47V-1.17V 32KB Timing Speculative SRAM in 28nm HKMG CMOS. 1-5 - Sumit Kumar, Nagesh Ch:
Design of a Two-Step Low-Power and High-Speed CMOS Flash ADC Architecture. 1-6 - Vivek Jaluka, Rajesh Kolluri
Virtual Droplet Routing Algorithm for Digital Microfluidic Biochips. 1-6 - Aparna Mishra, Anuj Grover
A 0.9V 64Mb 6T SRAM cell with Read and Write assist schemes in 65nm LSTP technology. 1-4 - Aryamick Singh, Kavindra Kandpal
Design of a Threshold Voltage Insensitive 3T1C Pixel Circuit Using a-IGZO TFT for AMOLED Displays. 1-5 - Nirmal Kumar Boran, Dinesh Kumar Yadav, Rishabh R. Iyer:
Classification based scheduling in Heterogeneous ISA Architectures. 1-6 - Arvind Thumatti K. R., Marcel Brand, Christian Heidorn, Srinivas Boppu, Frank Hannig, Jürgen Teich:
Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. 1-6 - Manpreet Kaur Jaswal, Subir Kumar Roy:
DynRP- Non-Intrusive Profiler for Dynamic Reconfigurability. 1-6 - Jai Gopal Pandey, Ayush Laddha, Sashwat Deb Samaddar:
A Lightweight VLSI Architecture for RECTANGLE Cipher and its Implementation on an FPGA. 1-6 - Jyotiranjan Swain
A Proactive Wash droplet routing for Digital Microfluidics Biochip. 1-4 - Hariveer Inumarty, M. Mohamed Asan Basiri
Reconfigurable Hardware Design for Polynomial Galois Field Arithmetic Operations. 1-5 - Pankaj Kumar Kalita, Ramanuj Chouksey, Chandan Karfa
Automatic Inverse Operation Detection and its Impact in High-level Synthesis. 1-4 - Mandakini Kadam, Saroja V. Siddamal, Shripadraj Annigeri:
Design and Implementation of chaotic nondeterministic random seed-based Hybrid True Random Number Generator. 1-5 - Suvadip Hazra
Design, Threat Analysis and Countermeasure for a Cache Performance Affecting Hardware Trojan. 1-6 - Kolluri Rajesh
Reinforcement Learning based Droplet Routing Algorithm for Digital Microfluidic Biochips. 1-6 - Ajish Zacharias, Gisha C. G.
Chaotic Ring Oscillator Based True Random Number Generator Implementations in FPGA. 1-6 - Vivian Desalphine, Somya Dashora, Laxita Mali, Suhas K, Aneesh Raveendran, David Selvakumar:
Novel Method for Verification and Performance Evaluation of a Non-Blocking Level-1 Instruction Cache designed for Out-of-Order RISC-V Superscaler Processor on FPGA. 1-4
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-15 19:20 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: