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ICCAD 2019: Westminster, CO, USA
- David Z. Pan:
Proceedings of the International Conference on Computer-Aided Design, ICCAD 2019, Westminster, CO, USA, November 4-7, 2019. ACM 2019, ISBN 9781728123509 - James Pond, Xu Wang, Zeqin Lu, Ellen Schelew, Gilles Lamant, Ahmadreza Farsaei:
Latest Advancements to the Industry-Leading EPDA Design Flow for Silicon Photonics: Invited Paper. 1-6 - Marleson Graf, Olav P. Henschel, Rafael P. Alevato, Luiz C. V. dos Santos
:
Spec&Check: An Approach to the Building of Shared-Memory Runtime Checkers for Multicore Chip Design Verification. 1-7 - Yi Cai, Xiaoming Chen, Lu Tian, Yu Wang, Huazhong Yang:
Enabling Secure in-Memory Neural Network Computing by Sparse Fast Gradient Encryption. 1-8 - Yonghwi Kwon, Inhak Han, Youngsoo Shin:
Clock Gating Synthesis of Netlist with Cyclic Logic Paths. 1-6 - Li-C. Wang, Chuanhe Jay Shan, Ahmed Wahba:
Facilitating Deployment Of A Wafer-Based Analytic Software Using Tensor Methods: Invited Paper. 1-8 - Zheng Zhao, Jiaqi Gu, Zhoufeng Ying, Chenghao Feng, Ray T. Chen, David Z. Pan:
Design Technology for Scalable and Robust Photonic Integrated Circuits: Invited Paper. 1-7 - Maryam Parsa
PABO: Pseudo Agent-Based Multi-Objective Bayesian Hyperparameter Optimization for Efficient Neural Accelerator Design. 1-8 - Nimisha Limaye, Abhrajit Sengupta, Mohammed Nabeel, Ozgur Sinanoglu
Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access. 1-8 - Qijing Huang
Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration. 1-8 - Kaveh Shamsi, David Z. Pan, Yier Jin
IcySAT: Improved SAT-based Attacks on Cyclic Locked Circuits. 1-7 - Scott Best, Xiaolin Xu:
An All-Digital True Random Number Generator Based on Chaotic Cellular Automata Topology. 1-8 - Yu-Hsuan Su, Richard Sun, Pei-Hsin Ho:
2019 CAD Contest: System-level FPGA Routing with Timing Division Multiplexing Technique. 1-2 - Yuan Cheng, Guangya Li, Ngai Wong, Hai-Bao Chen, Hao Yu:
DEEPEYE: A Deeply Tensor-Compressed Neural Network Hardware Accelerator: Invited Paper. 1-8 - Ghasem Pasandi, Massoud Pedram:
A Dynamic Programming-Based, Path Balancing Technology Mapping Algorithm Targeting Area Minimization. 1-8 - Zheyu Liu, Kaige Jia, Weiqiang Liu, Qi Wei, Fei Qiao, Huazhong Yang:
INA: Incremental Network Approximation Algorithm for Limited Precision Deep Neural Networks. 1-7 - Cong Hao, Yao Chen
NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving. 1-8 - Qian Wang, Tianyu Wang
Re-Tangle: A ReRAM-based Processing-in-Memory Architecture for Transaction-based Blockchain. 1-8 - Alwin Zulehner, Stefan Hillmich
How to Efficiently Handle Complex Values? Implementing Decision Diagrams for Quantum Computing. 1-7 - Qingcheng Xiao, Yun Liang:
Zac: Towards Automatic Optimization and Deployment of Quantized Deep Neural Networks on Embedded Devices. 1-6 - Jiameng Fan, Chao Huang, Wenchao Li, Xin Chen, Qi Zhu:
Towards Verification-Aware Knowledge Distillation for Neural-Network Controlled Systems: Invited Paper. 1-8 - Biying Xu, Keren Zhu
MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. 1-8 - Gyoung-Hwan Hyun, Taewhan Kim:
Flip-flop State Driven Clock Gating: Concept, Design, and Methodology. 1-6 - Kourosh Hakhamaneshi, Nick Werblun, Pieter Abbeel, Vladimir Stojanovic:
BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Networks. 1-8 - Yi-Chen Lu, Jeehyun Lee, Anthony Agnesina, Kambiz Samadi, Sung Kyu Lim
GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization. 1-8 - Gyoung-Hwan Hyun, Taewhan Kim:
Allocation of State Retention Registers Boosting Practical Applicability to Power Gated Circuits. 1-6 - Marvin Damschen
WCET Guarantees for Opportunistic Runtime Reconfiguration. 1-6 - Mengchu Li, Tsun-Ming Tseng
VOM: Flow-Path Validation and Control-Sequence Optimization for Multilayered Continuous-Flow Microfluidic Biochips. 1-8 - Vojtech Mrazek
ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. 1-8 - Xiao Shi, Hao Yan, Jiajia Zhang, Qiancun Huang, Longxing Shi, Lei He:
Efficient Yield Analysis for SRAM and Analog Circuits using Meta-Model based Importance Sampling Method. 1-8 - Max Willsey, Ashley P. Stephenson, Chris Takahashi, Bichlien H. Nguyen, Karin Strauss, Luis Ceze:
Scaling Microfluidics to Complex, Dynamic Protocols: Invited Paper. 1-6 - Ankit Wagle, Elham Azari, Sarma B. K. Vrudhula:
Embedding Binary Perceptrons in FPGA to improve Area, Power and Performance. 1-8 - Hyein Shin, Jaehyeong Sim
A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks. 1-8 - Tao Liu, Wujie Wen:
Making the Fault-Tolerance of Emerging Neural Network Accelerators Scalable. 1-5 - Haocheng Li
Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction. 1-7 - Wuxi Li, Yibo Lin, David Z. Pan:
elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs. 1-8 - Hai Zhou, Amin Rezaei, Yuanqi Shen:
Resolving the Trilemma in Logic Encryption. 1-8 - Po-Chun Chien
Time-Frame Folding: Back to the Sequentiality. 1-8 - Tingshen Lan, Xingquan Li
Timing-Aware Fill Insertions with Design-Rule and Density Constraints. 1-8 - Mohamed Ibrahim, Maria Gorlatova, Krishnendu Chakrabarty
The Internet of Microfluidic Things: Perspectives on System Architecture and Design Challenges: Invited Paper. 1-8 - Peng Cao, Zhiyuan Liu, Jiangping Wu, Jingjing Guo, Jun Yang, Longxing Shi:
A Statistical Timing Model for Low Voltage Design Considering Process Variation. 1-8 - Chunhua Deng, Miao Yin, Xiao-Yang Liu, Xiaodong Wang, Bo Yuan:
High-performance Hardware Architecture for Tensor Singular Value Decomposition: Invited Paper. 1-6 - Haowen Fang, Amar Shrestha, Ziyi Zhao, Yilan Li, Qinru Qiu:
An Event-driven Neuromorphic System with Biologically Plausible Temporal Dynamics. 1-8 - Wei-Chen Wang
Toward Instantaneous Sanitization through Disturbance-induced Errors and Recycling Programming over 3D Flash Memory. 1-8 - Qi Sun
Power-Driven DNN Dataflow Optimization on FPGA. 1-7 - Youngbeom Jung
eSRCNN: A Framework for Optimizing Super-Resolution Tasks on Diverse Embedded CNN Accelerators. 1-8 - Albert Magyar, David Biancolin, John Koenig, Sanjit Seshia, Jonathan Bachrach, Krste Asanovic:
Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes. 1-8 - Hao-Yu Chi, Zi-Jun Lin, Chia-Hao Hung, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines. 1-6 - Kai Lu, Zhaoshi Li, Leibo Liu
ReDESK: A Reconfigurable Dataflow Engine for Sparse Kernels on Heterogeneous Platforms. 1-8 - Zhan-Ling Wang, Yao-Wen Chang:
Graph- and ILP-Based Cut Redistribution for Two-Dimensional Directed Self-Assembly. 1-7 - Anthony Agnesina, Etienne Lepercq, Jose Escobedo, Sung Kyu Lim
Reducing Compilation Effort in Commercial FPGA Emulation Systems Using Machine Learning. 1-8 - Tsun-Ming Tseng
Wavelength-Routed Optical NoCs: Design and EDA - State of the Art and Future Directions: Invited Paper. 1-6 - Giulia Meuli, Mathias Soeken, Earl T. Campbell, Martin Roetteler
The Role of Multiplicative Complexity in Compiling Low $T$-count Oracle Circuits. 1-8 - Jonas Krautter, Dennis R. E. Gnad
Active Fences against Voltage-based Side Channels in Multi-Tenant FPGAs. 1-8 - Indranil Palit, Qiuwen Lou, Robert Perricone, Michael T. Niemier, Xiaobo Sharon Hu
A Uniform Modeling Methodology for Benchmarking DNN Accelerators. 1-7 - Florian Lonsing
Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED: Invited Paper. 1-8 - Shuai Li, Wei Tong, Jingning Liu, Bing Wu, Yazhi Feng:
Accelerating garbage collection for 3D MLC flash memory with SLC blocks. 1-8 - Alric Althoff, Jeremy Blackstone, Ryan Kastner
Holistic Power Side-Channel Leakage Assessment: Towards a Robust Multidimensional Metric. 1-8 - Weidong Cao
Neural Network-Inspired Analog-to-Digital Conversion to Achieve Super-Resolution with Low-Precision RRAM Devices. 1-7 - Gaurav Kolhe, Hadi Mardani Kamali, Miklesh Naicker, Tyler David Sheaves
Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality. 1-8 - Shaahin Angizi, Deliang Fan:
ReDRAM: A Reconfigurable Processing-in-DRAM Platform for Accelerating Bulk Bit-Wise Operations. 1-8 - Jörg Henkel, Hussam Amrouch
The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper. 1-6 - Kaiqi Zhang, Xiyuan Zhang, Zheng Zhang
Tucker Tensor Decomposition on FPGA. 1-8 - Tsun-Ming Tseng
Cloud Columba: Accessible Design Automation Platform for Production and Inspiration: Invited Paper. 1-6 - Jiayuan He, Martin Burtscher, Rajit Manohar, Keshav Pingali:
SPRoute: A Scalable Parallel Negotiation-based Global Router. 1-8 - Fan Chen, Wei Wen, Linghao Song
How to Obtain and Run Light and Efficient Deep Learning Networks. 1-5 - Sergei Dolgov, Alexander Volkov, Lutong Wang, Bangqi Xu:
2019 CAD Contest: LEF/DEF Based Global Routing. 1-4 - Hakki Mert Torun, Huan Yu, Nihar Dasari, Venkata Chaitanya Krishna Chekuri
A Spectral Convolutional Net for Co-Optimization of Integrated Voltage Regulators and Embedded Inductors. 1-8 - Chia-Tung Ho, Andrew B. Kahng:
IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop. 1-8 - Zhenhua Zhu, Mingyuan Ma, Jialong Liu, Liying Xu, Xiaoming Chen, Yuchao Yang, Yu Wang, Huazhong Yang:
A General Logic Synthesis Framework for Memristor-based Logic Design. 1-8 - Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran
SCRIP: Secure Random Clock Execution on Soft Processor Systems to Mitigate Power-based Side Channel Attacks. 1-7 - Muhammad Imran, Taehyun Kwon, Jung Min You, Joon-Sung Yang:
Flipcy: Efficient Pattern Redistribution for Enhancing MLC PCM Reliability and Storage Density. 1-7 - Liangda Fang, Biqing Fang, Hai Wan, Zeqi Zheng, Liang Chang, Quan Yu:
Tagged Sentential Decision Diagrams: Combining Standard and Zero-suppressed Compression and Trimming Rules. 1-8 - Sahand Salamat, Behnam Khaleghi, Mohsen Imani, Tajana Rosing:
Workload-Aware Opportunistic Energy Efficiency in Multi-FPGA Platforms. 1-8 - Nicolai Hähnle, Pietro Saccardi:
Global routing on rhomboidal tiles. 1-8 - Zhiqiang Que
Towards In-Circuit Tuning of Deep Learning Designs. 1-6 - Ivan De Oliveira Nunes, Karim Eldefrawy, Norrathep Rattanavipanon, Gene Tsudik:
PURE: Using Verified Remote Attestation to Obtain Proofs of Update, Reset and Erasure in low-End Embedded Systems. 1-8 - Siyuan Xu, Benjamin Carrión Schäfer:
Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models. 1-8 - Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo
DATC RDF-2019: Towards a Complete Academic Reference Design Flow. 1-6 - Chunfeng Cui, Cole Hawkins, Zheng Zhang
Tensor Methods for Generating Compact Uncertainty Quantification and Deep Learning Models. 1-6 - Shehzeen Hussain
FastWave: Accelerating Autoregressive Convolutional Neural Networks on FPGA. 1-8 - Yu-Hsuan Chang, Hsiang-Ting Wen, Yao-Wen Chang:
Obstacle-Aware Group-Based Length-Matching Routing for Pre-Assignment Area-I/O Flip-Chip Designs. 1-8 - Ramesh Kumar Sah, Hassan Ghasemzadeh:
Adar: Adversarial Activity Recognition in Wearables. 1-8 - Chak-Wa Pui, Evangeline F. Y. Young:
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. 1-8 - Hongzheng Chen
A Deep-Reinforcement-Learning-Based Scheduler for FPGA HLS. 1-8 - Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang
MAGNet: A Modular Accelerator Generator for Neural Networks. 1-8 - Gaurav Rajavendra Reddy, Kareem Madkour, Yiorgos Makris
Machine Learning-Based Hotspot Detection: Fallacies, Pitfalls and Marching Orders. 1-8 - Kyeonghan Kim, Hyein Shin, Jaehyeong Sim
An Energy-efficient Processing-in-memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAM. 1-8 - Jyotirmoy V. Deshmukh, James Kapinski, Tomoya Yamaguchi, Danil V. Prokhorov:
Learning Deep Neural Network Controllers for Dynamical Systems with Safety Guarantees: Invited Paper. 1-7 - Andrew B. Kahng:
Looking Into the Mirror of Open Source: Invited Paper. 1-8 - Debjyoti Bhattacharjee
MUQUT: Multi-Constraint Quantum Circuit Mapping on NISQ Computers: Invited Paper. 1-7 - Ulf Schlichtmann
Overview of 2019 CAD Contest at ICCAD. 1-2 - Huili Chen, Cheng Fu, Jishen Zhao, Farinaz Koushanfar
GenUnlock: An Automated Genetic Algorithm Framework for Unlocking Logic Encryption. 1-8 - Zhenyuan Ruan, Tong He, Jason Cong:
Analyzing and Modeling In-Storage Computing Workloads On EISC - An FPGA-Based System-Level Emulation Platform. 1-8 - Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang:
Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis. 1-6 - Ching-Yi Huang, Chi-An (Rocky) Wu, Tung-Yuan Lee, Chih-Jen (Jacky) Hsu, Kei-Yong Khoo:
2019 CAD Contest: Logic Regression on High Dimensional Boolean Space. 1-6 - Pai-Shun Ting, John P. Hayes:
Exploiting Randomness in Stochastic Computing. 1-6 - Zichang He, Weilong Cui, Chunfeng Cui, Timothy Sherwood
Efficient Uncertainty Modeling for System Design via Mixed Integer Programming. 1-8 - Bingzhe Li
HAML-SSD: A Hardware Accelerated Hotness-Aware Machine Learning based SSD Management. 1-8 - Zahi Moudallal, Valeriy Sukharev, Farid N. Najm:
Power Grid Fixing for Electromigration-induced Voltage Failures. 1-8 - Ghada Dessouky, Shaza Zeitouni, Ahmad Ibrahim, Lucas Davi, Ahmad-Reza Sadeghi:
CHASE: A Configurable Hardware-Assisted Security Extension for Real-Time Systems. 1-8 - Siang-Yun Lee
Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks. 1-8 - Zhifei Wang, Jun Feng
Systematic Exploration of High-Radix Integrated Silicon Photonic Switches for Datacenters. 1-8 - Walter Lau Neto, Max Austin, Scott Temple
LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper. 1-6 - Yuyang Wang
Task Mapping-Assisted Laser Power Scaling for Optical Network-on-Chips. 1-6 - ChengYue Gong, Zixuan Jiang
Mixed Precision Neural Architecture Search for Energy Efficient Deep Learning. 1-7 - Manupa Karunaratne, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh:
4D-CGRA: Introducing Branch Dimension to Spatio-Temporal Application Mapping on CGRAs. 1-8 - Yannan Nellie Wu, Joel S. Emer, Vivienne Sze:
Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs. 1-8 - Muhammad Yasin
SFLL-HLS: Stripped-Functionality Logic Locking Meets High-Level Synthesis. 1-4 - Monal Narasimhamurthy
Verifying Conformance of Neural Network Models: Invited Paper. 1-8 - Jungmin Park, Seongjoon Cho, Taejin Lim, Swarup Bhunia
SCR-QRNG: Side-Channel Resistant Design using Quantum Random Number Generator. 1-8 - Chih-Hong Cheng, Chung-Hao Huang, Georg Nührenberg:
nn-dependability-kit: Engineering Neural Networks for Safety-Critical Autonomous Driving Systems. 1-6 - Wei-Ming Chen, Yi-Ting Chen, Pi-Cheng Hsiu
Multiversion Concurrency Control on Intermittent Systems. 1-8 - Siad Daboul, Stephan Held, Bento Natura, Daniel Rotter:
Global Interconnect Optimization. 1-8 - Robert Wille, Majid Haghparast
Towards HDL-based Synthesis of Reversible Circuits with No Additional Lines. 1-7 - Bastian Richter, Alexander Wild, Amir Moradi
Automated Probe Repositioning for On-Die EM Measurements. 1-6 - Jianli Chen, Wenxing Zhu, Jun Yu, Lei He, Yao-Wen Chang:
Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs. 1-8 - Shashank Varshney, Hameedah Sultan, Palkesh Jain, Smruti R. Sarangi:
NanoTherm: An Analytical Fourier-Boltzmann Framework for Full Chip Thermal Simulations. 1-8 - Yintao He
An Agile Precision-Tunable CNN Accelerator based on ReRAM. 1-7 - Keren Zhu
GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. 1-8 - Mohsen Imani, Samuel Bosch
SemiHD: Semi-Supervised Learning Using Hyperdimensional Computing. 1-8 - Debayan Roy, Swaminathan Narayanaswamy, Alma Pröbstl, Samarjit Chakraborty
Multi-Stage Optimization for Energy-Efficient Active Cell Balancing in Battery Packs. 1-8 - Jinhie Skarda, Logan Su, Ki Youl Yang, Dries Vercruysse, Neil V. Sapra, Jelena Vuckovic
From Inverse Design to Implementation of Practical Photonics. 1-4 - Jai-Ming Lin, You-Lun Deng, Ya-Chu Yang, Jia-Jian Chen, Yao-Chieh Chen:
A Novel Macro Placement Approach based on Simulated Evolution Algorithm. 1-7 - Haobo Xu, Ying Wang, Yujie Wang, Jiajun Li, Bosheng Liu
ACG-Engine: An Inference Accelerator for Content Generative Neural Networks. 1-7 - Alejandro J. Calderón
Understanding and Exploiting the Internals of GPU Resource Allocation for Critical Systems. 1-8 - Radhakrishna Sanka
Specification, Integration, and Benchmarking of Continuous Flow Microfluidic Devices: Invited Paper. 1-8 - Xing Huang, Chi-Chun Liang, Jia Li, Tsung-Yi Ho
Open-Source Incubation Ecosystem for Digital Microfluidics - Status and Roadmap: Invited Paper. 1-6 - Patanjali SLPSK, Prasanna Karthik Vairam
Karna: A Gate-Sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack Protection. 1-8 - Zhengqi Gao, Jun Tao, Fan Yang, Yangfeng Su, Dian Zhou, Xuan Zeng:
Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network. 1-8 - Cheongwon Lee, Youngsoo Song, Youngsoo Shin:
Endurance Enhancement of Multi-Level Cell Phase Change Memory. 1-8 - Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev, Mahesh V. Tripunitara:
Strengthening PUFs using Composition. 1-8 - Simon Rokicki, Davide Pala, Joseph Paturel, Olivier Sentieys:
What You Simulate Is What You Synthesize: Designing a Processor Core from C++ Specifications. 1-8 - Yu-Guang Chen, Ing-Chao Lin, Jian-Ting Ke:
ROAD: Improving Reliability of Multi-core System via Asymmetric Aging. 1-8
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