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ICFPT 2023: Yokohama, Japan
- International Conference on Field Programmable Technology, ICFPT 2023, Yokohama, Japan, December 12-14, 2023. IEEE 2023, ISBN 979-8-3503-5911-4
- Nils Albartus, Maik Ender, Jan-Niklas Möller, Marc Fyrbiak, Christof Paar, Russell Tessier:
On the Malicious Potential of Xilinx' Internal Configuration Access Port (ICAP). 1 - Theodoros Trochatos, Anthony Etim, Jakub Szefer:
Covert-channels in FPGA-enabled SmartSSDs. 2 - Geng Yang, Jie Lei, Zhenman Fang, Yunsong Li, Jiaqing Zhang, Weiying Xie:
Journal Track Paper ICFPT 2023 : HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks. 3-4 - Emanuele Del Sozzo, Davide Conficconi, Kentaro Sano:
Journal Track Paper ICFPT 2023 : Across Time and Space: Senju's Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs. 5 - Tianyou Bao, Pengzhou He, Jiafeng Xie, H. S. Jacinto:
AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-based Lightweight PQC. 6 - Timothy Martin, Qi Li, Charlotte Barnes, Gary Gréwal, Shawki Areibi:
A Deep-Learning Data-Driven Approach for Reducing FPGA Routing Runtimes. 7-15 - Maximillian Panoff, Muhammed Kawser Ahmed, Hanqiu Wang, Shuo Wang, Christophe Bobda:
A Tenant Side Compilation Solution for Cloud FPGA Deployment. 16-25 - Jiangnan Li, Chang Cai, Yaya Zhao, Yazhou Yan, Wenbo Yin, Lingli Wang:
GRAFT: GNN-based Adaptive Framework for Efficient CGRA Mapping. 26-34 - Baoze Zhao, Wenjin Huang, Tianrui Li, Yihua Huang:
BSTMSM: A High-Performance FPGA-based Multi-Scalar Multiplication Hardware Accelerator. 35-43 - Timo Haarman, Antonio Sousa de Almeida, Amber Heskes, Floris Zwanenburg, Nikolaos Alachiotis:
FPGA-accelerated Quantum Transport Measurements. 44-52 - Zhengzheng Ma, Guojie Luo:
An Efficient Dataflow for Convolutional Generative Models. 53-59 - Marta Andronic, George A. Constantinides:
PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference. 60-68 - Yuzong Chen, Jordan Dotzel, Mohamed S. Abdelfattah:
M4BRAM: Mixed-Precision Matrix-Matrix Multiplication in FPGA Block RAMs. 69-78 - Kaichuang Shi, Hao Zhou, Lingli Wang:
VIB: A Versatile Interconnection Block for FPGA Routing Architecture. 79-87 - Jingyuan Li
, Yihan Hu, Yuan Dai
AUGER: A Multi-Objective Design Space Exploration Framework for CGRAs. 88-95 - Endri Taka, Aman Arora
MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine. 96-105 - Huizhen Kuang
HGBO-DSE: Hierarchical GNN and Bayesian Optimization based HLS Design Space Exploration. 106-114 - Robert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede:
A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis. 115-124 - Zibo Guo
Efficient FPGA-based Accelerator for Post-Processing in Object Detection. 125-131 - Mohamed Ibrahim, Zhipeng Zhao, Mathew Hall, Vaughn Betz:
Extending Data Flow Architectures for Convolutional Neural Networks to Multiple FPGAs. 132-141 - Reilly McKendrick, Keenan Faulkner, Jeffrey Goeders:
Assuring Netlist-to-Bitstream Equivalence using Physical Netlist Generation and Structural Comparison. 142-151 - Fatemehsadat Mahmoudi, Mohamed A. Elgammal, Soheil Gholami Shahrouz, Kevin E. Murray, Vaughn Betz:
Respect the Difference: Reinforcement Learning for Heterogeneous FPGA Placement. 152-160 - Qi Liu, Mo Sun, Jie Sun, Liqiang Lu, Jieru Zhao, Zeke Wang:
SSiMD: Supporting Six Signed Multiplications in a DSP Block for Low-Precision CNN on FPGAs. 161-169 - Kanta Yoshioka, Yuichiro Tanaka, Hakaru Tamukoh:
LUTNet-RC: Look-Up Tables Networks for Reservoir Computing on an FPGA. 170-178 - Alexander Montgomerie-Corcoran, Petros Toupas
SATAY: A Streaming Architecture Toolflow for Accelerating YOLO Models on FPGA Devices. 179-187 - Xiaobei Yan, Xiaoxuan Lou, Guowen Xu, Han Qiu, Shangwei Guo, Chip-Hong Chang, Tianwei Zhang:
MERCURY: An Automated Remote Side-channel Attack to Nvidia Deep Learning Accelerator. 188-197 - Andrew Boutros, Fatemehsadat Mahmoudi, Amin Mohaghegh, Stephen More, Vaughn Betz:
Into the Third Dimension: Architecture Exploration Tools for 3D Reconfigurable Acceleration Devices. 198-208 - Chia-Chen Yen, Mi-Yen Yeh, Ming-Syan Chen:
Integrated Multi-Ported Memory Distribution for Temporal-Multiplexing Workloads on FPGAs. 209-216 - Weihai Xu, Zheng Zhou, Jin Zhang, Yiming Jiang, Peng Yi:
OD-REM: On-Demand Regular Expression Matching on FPGAs for Efficient Deep Packet Inspection. 217-226 - Dongjoon Park
Asymmetry in Butterfly Fat Tree FPGA NoC. 227-231 - Frank Ridder, Kuan-Hsun Chen
Accelerated Real-Time Classification of Evolving Data Streams using Adaptive Random Forests. 232-237 - Mo Song, Jiajun Wu, Yuhao Ding, Hayden Kwok-Hay So:
SqueezeBlock: A Transparent Weight Compression Scheme for Deep Neural Networks. 238-243 - Philippos Papaphilippou
Efficiently Removing Sparsity for High-Throughput Stream Processing. 244-249 - Kaichuang Shi, Hao Zhou, Lingli Wang:
Explore the Feedback Interconnects in Intra-Cluster Routing for FPGAs. 250-253 - Tingting Qiao, Yu Xie
An FPGA-GPU Heterogeneous System and Implementation for On-Board Remote Sensing Data Processing. 254-257 - Ning Zhang, Shuo Ni, Tingting Qiao, Wenchao Liu, He Chen:
An Extremely Pipelined FPGA-based accelerator of All Adder Neural Networks for On-board Remote Sensing Scene Classification. 258-261 - Ryota Miyagi, Ryota Yasudo, Kentaro Sano, Hideki Takase:
Performance Modeling and Scalability Analysis of Stream Computing in ESSPER FPGA Clusters. 262-265 - Kanta Yoshioka, Yuichiro Tanaka, Hakaru Tamukoh:
Traffic Flow Optimization using a Chaotic Boltzmann Machine Annealer on an FPGA. 266-267 - Akinobu Tomori, Yasunori Osana:
Kyokko: a Virtual channel capable Aurora 64B/66B compatible Serial Communication Controller. 268-269 - Hayato Mori, Eisuke Okazaki, Gai Nagahashi, Mikiko Sato, Takeshi Ohkawa, Midori Sugaya:
Offloading Image Recognition Processing for Care Robots to FPGA on Multi-access Edge Computing. 270-271 - Kaijie Wei, Ryohei Niwase, Hideharu Amano, Yoshiki Yamaguchi, Takefumi Miyoshi:
A state vector quantum simulator working on FPGAs with extensible SATA storage. 272-273 - Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
Stochastic Implementation of Simulated Quantum Annealing on PYNQ. 274-275 - Yingchang Mao, Qiang Liu:
An FPGA-based Mix-grained Sparse Training Accelerator. 276-277 - Moucheng Yang, Kaixiang Zhu, Lingli Wang, Xuegong Zhou:
DSLUT: An Asymmetric LUT and its Automatic Design Flow Based on Practical Functions. 278-279 - Bizhao Shi, Jieran Zhang, Guojie Luo:
F-TFM: Accelerating Total Focusing Method for Ultrasonic Array Imaging on FPGA. 280-281 - Benjamin Ramhorst, Vladimir Loncar, George A. Constantinides:
FPGA Resource-aware Structured Pruning for Real-Time Neural Networks. 282-283 - Suquan Zhang, Jincheng Yu, Yuanfan Xu, Yu Wang:
UAV Swarm Planning accelerator on FPGA with low latency and fixed-point L-BFGS Quasi-Newton solver. 284-285 - Antonio Filgueras, Miquel Vidal, Daniel Jiménez-González, Carlos Álvarez
FPGA Framework Improvements for HPC Applications. 286-287 - Ryohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi, Kaijie Wei, Hideharu Amano, Takefumi Miyoshi:
Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storages. 288-289 - Edward Grindley, Thurstan Gray, James Wilkinson, Chris Vaux, Adam Ardron, Jack Deeley, Alexander Elliott, Nidhin Thandassery Sumithran
Introducing the NAIL Accelerator Interface Layer for Low Latency FPGA Offload. 290-291 - Zhenyu Wu
Towards Asynchronously Triggered Spiking Neural Network on FPGA for Event-based Vision. 292-293 - Zhen Li, Hao Zhou, Lingli Wang, Xuegong Zhou:
AMG: Automated Efficient Approximate Multiplier Generator for FPGAs via Bayesian Optimization. 294-295 - Yuhang Cao, Yunhui Qiu, Xuchen Gao
E2-ACE: An Energy-Efficient Reconfigurable Crypto-Accelerator with Agile End-to-End Toolchain. 296-297 - Qilong Zhu, Yuhang Cao, Yunhui Qiu, Xuchen Gao
A Dynamic Partial Reconfigurable CGRA Framework for Multi-Kernel Applications. 298-299 - Liangji Chen, Tingyuan Liang, Wei Zhang, Sharad Sinha:
DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis. 300-301 - Sujan Kumar Saha, Abigail N. Butka, Muhammed Kawser Ahmed, Christophe Bobda:
OpenTitan based Multi-Level Security in FPGA System-on-Chips. 302-303
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