default search action
30th FCCM 2022: New York City, NY, USA
- 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2022, New York City, NY, USA, May 15-18, 2022. IEEE 2022, ISBN 978-1-6654-8332-2
- Shengjun Xu, Wenjin Huang, Yihua Huang:
TFR-GCN: A GCN Accelerator with Tile-Fusing Strategy. 1 - Ralf Kundel, Leonhard Nobach, Hans-Joerg Kolbe, Tobias Meuser, Ralf Steinmetz
:
FPGA-assisted Massive Packet Queueing and Traffic Shaping at the Network Edge. 1 - Lina Sawalha, Tawfiq Abuaita, Martin Cowley, Sergei Akhmatdinov
Accurate Performance and Power Prediction for FPGAs Using Machine Learning. 1 - Xingyue Qian, Jian Shi, Li Shi, Haoyang Zhang, Lijian Bian, Weikang Qian:
Exploiting Scheduling Information for Efficient High-Level Synthesis Design Space Exploration. 1 - Tong Wu, Oliver Diessel:
Leveraging FPGA Runtime Reconfigurability to Implement Multi-Hash-Chain Proof-of-Work. 1-5 - Loïc Sylvestre, Jocelyn Sérot, Emmanuel Chailloux:
A Virtual Machine Approach for High-level FPGA Programming. 1 - Lewis D. McLaughlin, Louise H. Crockett, Robert W. Stewart:
A New Design Workflow for PYNQ Enabled Xilinx Platforms Utilising the Simulink Environment for Vivado IPI Abstraction. 1 - Lana Josipovic
Resource Sharing in Dataflow Circuits. 1-9 - Archit Gajjar
FAXID: FPGA-Accelerated XGBoost Inference for Data Centers using HLS. 1-9 - Martin Langhammer, Sergey Gribok, Bogdan Pasca
Low-Latency Modular Exponentiation for FPGAs. 1-9 - Mehdi Moghaddamfar, Christian Färber, Norman May, Wolfgang Lehner
FPGA-Based Database Query Processing on Arbitrarily Wide Tables. 1 - Jianyi Cheng, John Wickerson, George A. Constantinides:
Dynamic C-Slow Pipelining for HLS. 1-10 - Mengshu Sun
Hardware-Friendly Acceleration for Deep Neural Networks with Micro-Structured Compression. 1 - Junning Fan, Oliver Diessel:
On the Single Event Upset Vulnerability and Mitigation of Binarized Neural Networks on FPGAs. 1 - Sajjad Tamimi, Florian Stock, Andreas Koch, Arthur Bernhardt, Ilia Petrov:
An Evaluation of Using CCIX for Cache-Coherent Host-FPGA Interfacing. 1-9 - Najdet Charaf
MaNaBIT: A Versatile Tool for Manipulating and Analyzing FPGA Bitstreams. 1 - Vincent Meyers
Reverse Engineering Neural Network Folding with Remote FPGA Power Analysis. 1-10 - Yukui Luo, Shijin Duan, Cheng Gongye, Yunsi Fei, Xiaolin Xu:
NNReArch: A Tensor Program Scheduling Framework Against Neural Network Architecture Reverse Engineering. 1-9 - Yang Yang, Sanmukh R. Kuppannagari
FPGA Accelerator for Homomorphic Encrypted Sparse Convolutional Neural Network Inference. 1-9 - Nicolai Fiege
Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling. 1-2 - Maik Ender
A Cautionary Note on Protecting Xilinx' UltraScale(+) Bitstream Encryption and Authentication Engine. 1-9 - Nicholas Beckwith, Jialiang Zhang, Jing Jane Li:
Augmenting HLS with Zero-Overhead Application-Specific Address Mapping for Optane DCPMM. 1-9 - Ecenur Ustun, Ismail San, Jiaqi Yin, Cunxi Yu
IMpress: Large Integer Multiplication Expression Rewriting for FPGA HLS. 1-10 - Atiyehsadat Panahi, Ehsan Kabir, Austin R. J. Downey
High-Rate Machine Learning for Forecasting Time-Series Signals. 1-9 - Jihwan Cho, Dalta Imam Maulana, Wanyeong Jung
A Near-Memory Radix Sort Accelerator with Parallel 1-bit Sorter. 1 - Seyed Alireza Damghani, Kenneth B. Kent
Odin-II Partial Technology Mapping for Yosys Coarse-grained Netlists in VTR. 1 - Ruiqi Chen
Biological Activity Prediction of GPCR-targeting Ligands on Heterogeneous FPGA-based Accelerators. 1 - Jennifer Pearl Smith, John I. Bailey III, Benjamin A. Mazin:
Highly-Multiplexed Superconducting Detector Readout: Approachable High-Speed FPGA Design. 1-2 - Hanning Chen, Mohsen Imani:
Density-Aware Parallel Hyperdimensional Genome Sequence Matching. 1-4 - Tomoya Yokono, Yoshiro Yamabe, Kenji Tanaka, Yuki Arikawa, Teruaki Ishizaki:
FPGA-based Accelerators System with Low Latency Autonomous DMA Engine. 1 - Gyeongcheol Shin, Junsoo Kim, Joo-Young Kim:
OpenMDS: An Open-Source Shell Generation Framework for High-Performance Design on Multi-Die FPGAs. 1 - Xiang Li, Russell Tessier
Precise Fault Injection to Enable DFIA for Attacking AES in Remote FPGAs. 1-5 - Rushi Patel, Pouya Haghi, Shweta Jain, Andriy Kot, Venkata Krishnan, Mayank Varia, Martin C. Herbordt:
COPA Use Case: Distributed Secure Joint Computation. 1-2 - Yeo-Reum Park, Ji-Hoon Kim, Jaeyoung Do, Joo-Young Kim:
A Dual-Mode Similarity Search Accelerator based on Embedding Compression for Online Cross-Modal Image-Text Retrieval. 1-9 - Thomas Mauldin, Zhenyu Xu, Tao Wei:
Software defined optical time-domain reflectometer. 1-5 - Louis Ledoux
A Generator of Numerically-Tailored and High-Throughput Accelerators for Batched GEMMs. 1-10 - Saeid Gorgin, MohammadHosein Gholamrezaei, Danial Javaheri
An Efficient FPGA Implementation of k-Nearest Neighbors via Online Arithmetic. 1-2 - Nick Brown
A programming model for developing Application Specific Dataflow Machines on FPGAs. 1 - Yuan Meng
Accelerating Deformable Convolution Networks. 1 - Sajjad Rostami Sani, Anas Razzaq, Andy Gean Ye:
Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm. 1-9 - Aman Arora
CoMeFa: Compute-in-Memory Blocks for FPGAs. 1-9 - Cornelia Wulf, Najdet Charaf
Scheduling of Hardware Tasks in Reconfigurable Mixed-Criticality Systems. 1 - Tiancheng Xu
An FPGA Accelerator for Genome Variant Calling. 1-9 - Stewart Denholm, Wayne Luk:
Mixed-Resource Parallel Processing on FPGAs. 1 - Jens Trautmann
Characterization of Side Channels on FPGA-based Off-The-Shelf Boards against Automated Attacks. 1-9 - Guiming Wu, Qianwen He, Jiali Jiang, Zhenxiang Zhang, Xin Long, Yuan Zhao, Yinchao Zou:
A High-Performance Hardware Architecture for ECC Point Multiplication over Curve25519. 1-9 - Anqi Guo, Tong Geng, Yongan Zhang, Pouya Haghi, Chunshu Wu, Cheng Tan, Yingyan Lin, Ang Li, Martin C. Herbordt:
FCsN: A FPGA-Centric SmartNIC Framework for Neural Networks. 1-2 - Yun Wang, Qiang Liu, Shun Yan:
DQI: A Dynamic Quantization Method for Efficient Convolutional Neural Network Inference Accelerators. 1 - Suhail Basalama, Atefeh Sohrabizadeh, Jie Wang, Jason Cong:
A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA. 1-2 - Srinirdheeshwar Kuttuva Prakash, Hiren D. Patel, Nachiket Kapre:
Managing HBM Bandwidth on Multi-Die FPGAs with FPGA Overlay NoCs. 1-9 - Michalis Pardalos
Resource Sharing for Verified High-Level Synthesis. 1-6 - Weikang Qiao, Licheng Guo, Zhenman Fang, Mau-Chung Frank Chang, Jason Cong:
TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs. 1 - Yutaka Urino, Takanori Shimizu, Hiroshi Yamaguchi, Kenji Mizutani, Shigeru Nakamura, Tatsuya Usuki, Michihiro Koibuchi:
A Scalable Distributed Radix Sorter for FPGA Clusters using High-Bandwidth Memory Networks. 1 - Peng Xue, Lunshuai Pan, Litao Sun, Mingqiang Huang:
Dual-Line-Systolic Array for High Performance CNN Accelerator. 1 - Johannes de Fine Licht, Christopher A. Pattison, Alexandros Nikolaos Ziogas
Fast Arbitrary Precision Floating Point on FPGA. 1-9
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-22 19:31 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: