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24th ETS 2019: Baden-Baden, Germany
- 24th IEEE European Test Symposium, ETS 2019, Baden-Baden, Germany, May 27-31, 2019. IEEE 2019, ISBN 978-1-7281-1173-5
- Jung-Geun Park, Minsu Kim, Soo-Mook Moon, Sungyeol Kim, Insu Yang, Hyunsoo Jung:
PaTran: Translation Platform for Test Pattern Program. 1-2 - Mahsa Akhsham, Atefesadat Seyedolhosseini, Zainalabedin Navabi:
Test Adapted Shielding by a Multipurpose Crosstalk Avoidance Scheme. 1-2 - Sebastian Huhn, Daniel Tille, Rolf Drechsler
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Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns. 1-2 - Xijiang Lin, Sudhakar M. Reddy:
On Generating Fault Diagnosis Patterns for Designs with X Sources. 1-6 - Soumya Mittal
LearnX: A Hybrid Deterministic-Statistical Defect Diagnosis Methodology. 1-6 - Leon M. A. van de Logt, Vladimir A. Zivkovic, Ingrid H. A. van Baast:
Model-driven AMS Test Setup Validation Tool prepared for IEEE P1687.2. 1-6 - Vaishali H. Dhare, Usha Mehta
Test Pattern Generator for Majority Voter based QCA Combinational Circuits targeting MMC Defect. 1-2 - Arjun Chaudhuri, Sanmitra Banerjee, Heechun Park, Bon Woong Ku, Krishnendu Chakrabarty
Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs. 1-6 - Yu Huang, Jakub Janicki, Szczepan Urban:
Non-Adaptive Pattern Reordering to Improve Scan Chain Diagnostic Resolution. 1-6 - Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Moritz Fieback
DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs. 1-2 - Lizhou Wu, Siddharth Rao
Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing. 1-6 - Luciano Bonaria, Maurizio Raganato, Matteo Sonza Reorda
A Dynamic Greedy Test Scheduler for Optimizing Probe Motion in In-Circuit Testers. 1-2 - Panagiotis Georgiou, Iakovos Theodosopoulos, Xrysovalantis Kavousianos:
K3 TAM Optimization for Testing 3D-SoCs using Non-Regular Time-Division-Multiplexing. 1-6 - Michele Portolan
A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks. 1-2 - Alessandro Savino
Approximate computing design exploration through data lifetime metrics. 1-7 - Freddy Forero, Michel Renovell, Víctor H. Champac:
B-open: A New Defect in Nanometer Technologies due to SADP Process. 1-2 - Görschwin Fey
Symbolic Circuit Analysis under an Arc Based Timing Model. 1-2 - Adeboye Stephen Oyeniran, Raimund Ubar
High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. 1-6 - Corrado De Sio
On the Evaluation of the PIPB Effect within SRAM-based FPGAs. 1-2 - Dominik Sisejkovic
Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries. 1-6 - A. Manzini, P. Inglese, L. Caldi, R. Cantero, G. Carnevale, M. Coppetta, M. Giltrelli, N. Mautone, F. Irrera, Rudolf Ullmann, Paolo Bernardi
A Machine Learning-based Approach to Optimize Repair and Increase Yield of Embedded Flash Memories in Automotive Systems-on-Chip. 1-6 - Imed Jani, Didier Lattard, Pascal Vivet
Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning. 1-2 - Hani Malloug, Manuel J. Barragán, Salvador Mir:
A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology. 1-6 - Mehmet Ince, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, LeRoy Winemberg, Sule Ozev:
Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection. 1-6 - Daniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor:
Hardware-Based Aging Mitigation Scheme for Memory Address Decoder. 1-6 - Jan Schat, Ulrich Möhlmann:
Concurrent Estimation of a PLL Transfer Function by Cross-Correlation with pseudo-random Jitter. 1-2 - Ghazanfar Ali, Jerrin Pathrose, Hans G. Kerkhoff:
IJTAG Compatible Timing Monitor with Robust Self-Calibration for Environmental and Aging Variation. 1-6 - T. Vayssade, Florence Azaïs, Laurent Latorre, Francois Lefevre:
Power Measurement and Spectral Test of ZigBee Transmitters from 1-bit Under-sampled Acquisition. 1-6 - Utkarsh Gupta, Priyank Kalla, Irina Ilioaea, Florian Enescu
Exploring Algebraic Interpolants for Rectification of Finite Field Arithmetic Circuits with Gröbner Bases. 1-6 - Foisal Ahmed
Feature Engineering for Recycled FPGA Detection Based on WID Variation Modeling. 1-2 - Benjamin Thiemann, Linus Feiten, Pascal Raiola, Bernd Becker
On Integrating Lightweight Encryption in Reconfigurable Scan Networks. 1-6 - Ruijun Ma
STAHL: A Novel Scan-Test-Aware Hardened Latch Design. 1-6 - Aleksa Damljanovic, Artur Jutman
Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks. 1-6 - Harshad Dhotre, Stephan Eggersglüß, Krishnendu Chakrabarty
Machine Learning-based Prediction of Test Power. 1-6 - Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi:
Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling. 1-6 - Nimisha Limaye, Muhammad Yasin
Revisiting Logic Locking for Reversible Computing. 1-6 - Fotis Foukalas, Paul Pop
Dependable Wireless Industrial IoT Networks: Recent Advances and Open Challenges. 1-10 - Stefan Katzenbeisser, Ilia Polian, Francesco Regazzoni
Security in Autonomous Systems. 1-8 - Yue Tian, Gaurav Veda, Wu-Tung Cheng, Manish Sharma, Huaxing Tang, Neerja Bawaskar, Sudhakar M. Reddy:
A supervised machine learning application in volume diagnosis. 1-6 - Fernando Fernandes dos Santos
Impact of Reduced Precision in the Reliability of Deep Neural Networks for Object Detection. 1-6 - Michele Portolan
Alternatives to Fault Injections for Early Safety/Security Evaluations. 1-10
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