default search action
DSD 2015: Madeira, Portugal
- 2015 Euromicro Conference on Digital System Design, DSD 2015, Madeira, Portugal, August 26-28, 2015. IEEE Computer Society 2015, ISBN 978-1-4673-8035-5
RECONFIG-1: Reconfigurable Computing (1)
- Vlastimil Kosar
, Jan Korenek:
Towards Efficient Field Programmable Pattern Matching Array. 1-8 - Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira
An FPGA Framework for Genetic Algorithms: Solving the Minimum Energy Broadcast Problem. 9-16
ADES: Analysis and Design of Embedded Systems
- Mladen Skelin, Marc Geilen
Worst-Case Throughput Analysis of SDF-Based Parametrized Dataflow. 17-24 - Reinier van Kampenhout, Sander Stuijk
A Scenario-Aware Dataflow Programming Model. 25-32 - Ashraf El Antably, Nicolas Fournel, Frédéric Rousseau:
Integrating Task Migration Capability in Software Tool-Chain for Data-Flow Applications Mapped on Multi-tiled Architectures. 33-40 - George Kornaros
Hardware Support for Cost-Effective System-Level Protection in Multi-core SoCs. 41-48
AIGP: Advanced Image and Graphics Processing
- Panu Sjovall
High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA. 49-56 - Silvia Franchini
Accelerating Clifford Algebra Operations Using GPUs and an OpenCL Code Generator. 57-64 - Tiago Rodrigues, Mário P. Véstias
Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGA. 65-71
SYNVER: Circuit Synthesis and Verification
- Anna Bernasconi, Robert K. Brayton, Valentina Ciriani, Gabriella Trucco, Tiziano Villa:
Bi-Decomposition Using Boolean Relations. 72-78 - Matheus Gibiluka, Matheus Trevisan Moreira, Ney Laert Vilar Calazans
A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework. 79-86 - Marcela Simková, Zdenek Kotásek:
Automation and Optimization of Coverage-driven Verification. 87-94
ASAIT: Architectures and Systems for Automotive and Intelligent Transportation
- Matthias Becker, Dakshina Dasari, Vincent Nélis
Investigation on AUTOSAR-Compliant Solutions for Many-Core Architectures. 95-103 - Victor Wilson Goncalves Azevedo, João Dionísio Simões Barros
Distributed Parallel Computing with Low Cost Microcontrollers for High Performance Electric Vehicles. 104-110
EPDSD-1: European Projects in Digital System Design (1)
- Giuseppe Massari
Harnessing Performance Variability: A HPC-Oriented Application Scenario. 111-116 - Carlos Álvarez
The AXIOM Software Layers. 117-124 - Werner Weber, Alfred Hoess, Frank Oppenheimer, Bernd Koppenhoefer, Bastijn Vissers, Bjørn Nordmoen:
EMC2 a Platform Project on Embedded Microcontrollers in Applications of Mobility, Industry and the Internet of Things. 125-130
FDR: Flexible Digital Radio
- Diogo Riscado, Jorge Santos, Daniel C. Dinis, Gustavo Anjos
A Flexible Research Testbed for C-RAN. 131-138 - Eren Unlu, Christophe Moy
Reconfigurable Traffic-Aware Radio Interconnect for a 2048-core Chip Multiprocessor. 139-145 - Andre Prata, Arnaldo S. R. Oliveira
An Agile and Wideband All-Digital SDR Receiver for 5G Wireless Communications. 146-151
EPDSD-2: European Projects in Digital System Design (2)
- Réda Nouacer, Manel Djemal, Smaïl Niar, Gilles Mouchard, Nicolas Rapin, Jean-Pierre Gallois, Philippe Fiani, Francois Chastrette, Toni Adriano, Bryan MacEachen:
Enhanced Quality Using Intensive Test and Analysis on Simulators. 152-157 - Giovanni Agosta
Playful Supervised Smart Spaces (P3S) - A Framework for Designing, Implementing and Deploying Multisensory Play Experiences for Children with Special Needs. 158-164
ASHWPA-1: Advanced Systems in Healthcare, Wellness, and Personal Assistance (1)
- Jose Angel Miguel
Implantable MEMS Pressure Sensors Modelling Tool. 165-172 - Alair Dias Junior, Srinivasan Murali, Francisco J. Rincón, David Atienza:
Estimation of Blood Pressure and Pulse Transit Time Using Your Smartphone. 173-180
DTFT-1: Dependability, Testing, and Fault Tolerance in Digital Systems (1)
- Varadan Savulimedu Veeravalli, Andreas Steininger
Reliable and Continuous Measurement of SET Pulse Widths. 181-188 - Thomas Polzer, Andreas Steininger
Measuring the Distribution of Metastable Upsets over Time. 189-196 - Marcel Baláz, Stefan Kristofík
Generic Self Repair Architecture with Multiple Fault Handling Capability. 197-204 - Tomas Vanat
A System for Radiation Testing and Physical Fault Injection into the FPGAs and Other Electronics. 205-210
ETCS: Emerging Technologies and Circuit Synthesis
- Anna Bernasconi, Valentina Ciriani, Gabriella Trucco
Biconditional-BDD Ordering for Autosymmetric Functions. 211-217 - Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian
Enhanced Spin-Diode Synthesis Using Logic Sharing. 218-224
SDSG-1: System Design for the Smart Grid (1)
- Vadim Alimguzhin, Federico Mari
A Glimpse of SmartHG Project Test-bed and Communication Infrastructure. 225-232 - Rune Hylsberg Jacobsen, Søren Aagaard Mikkelsen, Niels Holm Rasmussen:
Towards the Use of Pairing-Based Cryptography for Resource-Constrained Home Area Networks. 233-240 - Gilbert Maître, Gillian Basso, Claudio Steiner, Dominique Gabioud, Pierre Roduit:
Distributed Grid Storage by Ordinary House Heating Variations: A Swiss Case Study. 241-249
Posters 1
- Hrishikesh Salunkhe
Buffer Allocation for Dynamic Real-Time Streaming Applications Running on a Multi-processor without Back-Pressure. 250-254 - Joao Gabriel Reis, Lucas Francisco Wanner
A Framework for Dynamic Real-Time Reconfiguration. 255-258 - Adam Klimowicz
Minimization Method of Finite State Machines for Low Power Design. 259-262 - Helio Fernandes da Cunha Junior, Bruno de Abreu Silva, Vanderlei Bonato
Parameterizable Ethernet Network-on-Chip Architecture on FPGA. 263-266 - Selma Saidi, Yliès Falcone:
Dynamic Detection and Mitigation of DMA Races in MPSoCs. 267-270 - Waheed Ahmad
Green Computing: Power Optimisation of VFI-Based Real-Time Multiprocessor Dataflow Applications. 271-275 - Hossein Moradian, Jeong-A Lee:
Low-Cost Fault Localization and Error Correction for a Signed Digit Adder Design Utilizing the Self-Dual Concept. 276-279 - Jan Belohoubek
Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy. 280-283 - Ondrej Cekan
Software Fault Tolerance: The Evaluation by Functional Verification. 284-287 - Pietro Saltarelli, Behrad Niazmand
A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers. 288-292 - Pietro Dell'Acqua, Francesco Bellotti, Riccardo Berta
Safe Drive Map Concept for Road Curve Monitoring. 293-296 - Oussama Smiai, Francesco Bellotti, Alessandro De Gloria, Riccardo Berta
Information and Communication Technology Research Opportunities in Dynamic Charging for Electric Vehicle. 297-300 - Søren Aagaard Mikkelsen, Rune Hylsberg Jacobsen:
Consumer-Centric and Service-Oriented Architecture for the Envisioned Energy Internet. 301-305
POWER: Power Design
- Matteo Ferroni, Alessandro Antonio Nacci, Matteo Turri, Marco Domenico Santambrogio, Donatella Sciuto:
Experimental Evaluation and Modeling of Thermal Phenomena on Mobile Devices. 306-313 - Arghavan Asad, Ozcan Ozturk, Mahmood Fathy
Exploiting Heterogeneity in Cache Hierarchy in Dark-Silicon 3D Chip Multi-processors. 314-321
RECONFIG-2: Reconfigurable Computing (2)
- Ayan Palchaudhuri
Automated Design of High Performance Integer Arithmetic Cores on FPGA. 322-329 - João Pinhão, Wilson José, Horácio C. Neto
Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture. 330-336 - Oliver Knodel
Computing Framework for Dynamic Integration of Reconfigurable Resources in a Cloud. 337-344 - Valery Sklyarov, Iouliia Skliarova, João Paulo Sá da Silva, Alexander Sudnitson:
Analysis and Comparison of Attainable Hardware Acceleration in All Programmable Systems-on-Chip. 345-352
TSTVER: Test and Verification
- Yong Zhao, Hans G. Kerkhoff:
Unit-Based Functional IDDT Testing for Aging Degradation Monitoring in a VLIW Processor. 353-358 - Nils Przigoda
Leveraging the Analysis for Invariant Independence in Formal System Models. 359-366 - Ibrahima Diop, Pierre-Yvan Liardet, Yanis Linge, Philippe Maurine:
Collision Based Attacks in Practice. 367-374 - Nils Przigoda
Verification-Driven Design Across Abstraction Levels: A Case Study. 375-382
ASHWPA-2: Advanced Systems in Healthcare, Wellness, and Personal Assistance (2)
- Lang Yang, Thomas W. Chen:
A Low Power 64-point Bit-Serial FFT Engine for Implantable Biomedical Applications. 383-389 - François Patou
A Smart Mobile Lab-on-Chip-Based Medical Diagnostics System Architecture Designed for Evolvability. 390-398 - Joao Ricardo Borges dos Santos, Gabriel Blard, Arnaldo Silva Rodrigues de Oliveira
Wireless Sensor Tag and Network for Improved Clinical Triage. 399-406
AHSA-1: Architectures and Hardware for Security Applications (1)
- Duhyun Jeon, Jong-Hak Baek, Dong Kyue Kim, Byong-Deok Choi:
Towards Zero Bit-Error-Rate Physical Unclonable Function: Mismatch-Based vs. Physical-Based Approaches in Standard CMOS Technology. 407-414 - Xuan Thuy Ngo, Zakaria Najm, Shivam Bhasin, Debapriya Basu Roy, Jean-Luc Danger, Sylvain Guilley:
Integrated Sensor: A Backdoor for Hardware Trojan Insertions? 415-422 - Hermann Seuschek, Stefan Rass
Side-Channel Leakage Models for RISC Instruction Set Architectures from Empirical Data. 423-430 - Apostolos P. Fournaris, Odysseas G. Koufopavlou:
Affine Coordinate Binary Edwards Curve Scalar Multiplier with Side Channel Attack Resistance. 431-437
DTFT-2: Dependability, Testing, and Fault Tolerance in Digital Systems (2)
- Alistair A. McEwan
On-Line Device Replacement Techniques for SSD RAID. 438-444 - Mohsen Raji
Gate Resizing for Soft Error Rate Reduction in Nano-scale Digital Circuits Considering Process Variations. 445-452
MCSDIA-1: Mixed Criticality System Design, Implementation, and Analysis (1)
- Michael Paulitsch, Oscar Medina Duarte, Hassen Karray, Kevin Mueller, Daniel Münch, Jan Nowotsch:
Mixed-Criticality Embedded Systems - A Balance Ensuring Partitioning and Performance. 453-461 - Milos Panic
Enabling TDMA Arbitration in the Context of MBPTA. 462-469
SDSG-2: System Design for the Smart Grid (2)
- Rune Hylsberg Jacobsen, Dominique Gabioud, Gillian Basso, Pierre-Jean Alet, Armin Ghasem Azar
SEMIAH: An Aggregator Framework for European Demand Response Programs. 470-477 - Toni Mancini
User Flexibility Aware Price Policy Synthesis for Smart Grids. 478-485 - Gillian Basso, Pierre Ferrez, Dominique Gabioud, Pierre Roduit:
An Extensible Simulator for Dynamic Control of Residential Area: Case Study on Heating Control. 486-493 - Vasileios Botsis, Nikolaos D. Doulamis, Anastasios D. Doulamis, Prodromos Makris, Emmanouel A. Varvarigos
Efficient Clustering of DERs in a Virtual Association for Profit Optimization. 494-501
DHCPS: Design of Heterogeneous Cyber-Physical Systems
- Juan Valencia, Dip Goswami, Kees Goossens:
Composable Platform-Aware Embedded Control Systems on a Multi-core Architecture. 502-509 - Ghazaleh Nazarian, Razvan Nane
Low-Cost Software Control-Flow Error Recovery. 510-517 - Calypso Barnes, Jean-Marie Cottin, Davide Quaglia
Network-Aware Virtual Platform for the Verification of Embedded Software for Communications. 518-525
Posters 2
- Andrea Mondelli, Nam Ho, Alberto Scionti, Marco Solinas, Antoni Portero
Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions. 526-529 - Andrea Höller, Armin Krieg, Tobias Rauter, Johannes Iber, Christian Kreiner
QEMU-Based Fault Injection for a System-Level Analysis of Software Countermeasures Against Fault Attacks. 530-533 - Sebastian Reiter, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel:
White-Box Error Effect Simulation for Assisted Safety Analysis. 534-538 - Alejandro Nicolás, Pablo Sanchez:
Parallel Native-Simulation for Multi-processing Embedded Systems. 543-546 - Paris Kitsos
A Comparison of TERO and RO Timing Sensitivity for Hardware Trojan Detection Applications. 547-550 - Zoya Dyka, Christian Wittke, Peter Langendörfer:
Clockwise Randomization of the Observable Behaviour of Crypto ASICs to Counter Side Channel Attacks. 551-554 - João Carlos Bittencourt
CLEFIA Implementation with Full Key Expansion. 555-558 - Durga Prasad Sahoo, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay:
Towards Ideal Arbiter PUF Design on Xilinx FPGA: A Practitioner's Perspective. 559-562 - Christopher Scaffidi, Laurel Kincl, Diana Rohlman, Kim Anderson:
Linking the Physical with the Perceptual: Health and Exposure Monitoring with Cyber-physical Questionnaires. 563-566 - José Machado da Silva
Design for Dependability and Autonomy of a Wearable Cardiac and Coronary Monitor. 567-570 - Asier Larrucea, Jon Pérez
A Modular Safety Case for an IEC-61508 Compliant Generic Hypervisor. 571-574
ACCEL: Application-Specific Accelerators
- Alistair A. McEwan
An Embedded FTL for SSD RAID. 575-582 - Evangelos Koutsouradis, George Provelengios, Elias Kouskoumvekakis, Elias S. Manolakos:
Scalable FPGA Accelerator of the NRM Algorithm for Efficient Stochastic Simulation of Large-Scale Biochemical Reaction Networks. 583-590 - Runbin Shi, Zheng Xu, Zhihao Sun, Maurice Peemen, Ang Li, Henk Corporaal, Di Wu:
A Locality Aware Convolutional Neural Networks Accelerator. 591-598
SOCNOC: Systems and Networks on Chip
- Qiang Liu, Haie Li:
Hardware Design Space Exploration with a New Dimension - IP Protection Robustness. 599-605 - Davide Zoni
TEST: Assessing NoC Policies Facing Aging and Leakage Power. 606-613 - Hend Affes, Michel Auguin:
SOC Power Management Strategy Based on Global Hardware Functional State Analysis. 614-620 - Michael Vonbun, Stefan Wallentowitz
An Analytic Approach on End-to-End Packet Error Rate Estimation for Network-on-Chip. 621-628
MSDA: Multicore Systems: Design and Appplications
- Gorka Irazoqui, Thomas Eisenbarth
Systematic Reverse Engineering of Cache Slice Selection in Intel Processors. 629-636 - Antonio Miele
A System-Level Simulation Framework for Evaluating Resource Management Policies for Heterogeneous System Architectures. 637-644
AHSA-2: Architectures and Hardware for Security Applications (2)
- Hannes Groß, Erich Wenger, Christoph Dobraunig
Suit up! - Made-to-Measure Hardware Implementations of ASCON. 645-652 - Danuta Pamula, Arnaud Tisserand:
Fast and Secure Finite Field Multipliers. 653-660 - Markus Stefan Wamser, Lukas Holzbaur, Georg Sigl:
A Petite and Power Saving Design for the AES S-Box. 661-667 - Muhammad Hassan, Ayesha Khalid, Anupam Chattopadhyay, Christian Rechberger, Tim Güneysu
New ASIC/FPGA Cost Estimates for SHA-1 Collisions. 669-676
MCSDIA-2: Mixed Criticality System Design, Implementation, and Analysis (2)
- Irune Agirre
IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis. 677-684 - Milos Panic
CAP: Communication-Aware Allocation Algorithm for Real-Time Parallel Applications on Many-Cores. 685-692 - Hamidreza Ahmadian, Roman Obermaisser:
Time-Triggered Extension Layer for On-Chip Network Interfaces in Mixed-Criticality Systems. 693-699
DTFT-3: Dependability, Testing, and Fault Tolerance in Digital Systems (3)
- Raimund Ubar
Double Phase Fault Collapsing with Linear Complexity in Digital Circuits. 700-705 - Erol Koser, Felix Miller, Walter Stechele:
Matching Detection and Correction Schemes for Soft Error Handling in Sequential Logic. 706-713 - Nanditha P. Rao, Madhav P. Desai:
A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients. 714-721 - Thomas Polzer, Andreas Steininger
Enhanced Metastability Characterization Based on AC Analysis. 722-729
EPDSD-3: European Projects in Digital System Design (3)
- Werner Rom, Peter Priller, Jani Koivusaari, Maarjana Komi, Ramiro Robles, Luis Dominguez, Javier Rivilla, Willem D. van Driel:
DEWI - Wirelessly into the Future. 730-739 - Egidio D'Angelo
The Human Brain Project: High Performance Computing for Brain Cells Hw/Sw Simulation and Understanding. 740-747 - Vincent Nélis
Methodologies for the WCET Analysis of Parallel Applications on Many-Core Architectures. 748-755
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-22 19:31 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: