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16th DDECS 2013: Karlovy Vary, Czech Republic
- Lukás Sekanina, Görschwin Fey, Jaan Raik, Snorre Aunet, Richard Ruzicka:
16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013. IEEE Computer Society 2013, ISBN 978-1-4673-6135-4 - Foreword to the 16th IEEE DDECS Symposium.
- Rolf Drechsler
, Mathias Soeken
Hardware-Software Co-Visualization: Developing systems in the holodeck. 1-4 - Kaushik Roy:
Approximate computing for energy-efficient error-resilient multimedia systems. 5-6 - Erik Jan Marinissen:
Creating options for 3D-SIC testing. 7 - Grigory Fedyukovich, Antti E. J. Hyvärinen, Natasha Sharygina
Interpolation-based model checking for efficient incremental analysis of software. 8-9 - Mehdi Baradaran Tahoori:
Cross-layer resilient system design. 10 - Jan Korenek:
Hardware acceleration in computer networks. 11 - Ilia Polian, Martin Kreuzer
Fault-based attacks on cryptographic hardware. 12-17 - Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal:
Exploring processor parallelism: Estimation methods and optimization strategies. 18-23 - Josef Strnadel:
On design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systems. 24-29 - Danuta Pamula, Edward Hrynkiewicz:
Area-speed efficient modular architecture for GF(2m) multipliers dedicated for cryptographic applications. 30-35 - Stefano Di Carlo
On the on-line functional test of the Reorder Buffer memory in superscalar processors. 36-41 - Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke:
Fault collapsing of multi-conditional faults. 42-47 - Mehdi Dehbashi, Görschwin Fey
Efficient automated speedpath debugging. 48-53 - Mikhail J. Moiseev, Mikhail Glukhikh, Alexey V. Zakharov, Harald Richter:
A static analysis approach to data race detection in SystemC designs. 54-59 - Alexander Finder, Jan-Philipp Witte, Görschwin Fey
Debugging HDL designs based on functional equivalences with high-level specifications. 60-65 - Te-Hsuan Chen, John P. Hayes:
Design of stochastic Viterbi decoders for convolutional codes. 66-71 - Mohamed Atef
10Gb/s inverter based cascode transimpedance amplifier in 40nm CMOS technology. 72-75 - Hong Chen, Vladimir M. Milovanovic, Dario Giotta, Horst Zimmermann
Ultra-high bandwidth fully-differential three-stage operational amplifiers in 40nm digital CMOS. 76-81 - Yu-Lung Lo, Jhih-Wei Tsai, Han-Ying Liu, Wei-Bin Yang:
A GHz full-division-range programmable divider with output duty-cycle improved. 82-85 - Milica Orlandic
An area efficient hardware architecture design for H.264/AVC intra prediction reconstruction path based on partial reconfiguration. 86-91 - Filip Kadlcek, Otto Fucík:
Automatic synthesis of small AdaBoost classifier in FPGA. 92-97 - Yo-Hao Tu, Kuo-Hsing Cheng, Hsiang-Yun Wei, Hong-Yi Huang:
A low jitter delay-locked-loop applied for DDR4. 98-101 - Kamil Gomina, Jean-Baptiste Rigaud
Power analysis methodology for secure circuits. 102-107 - Jirí Matousek, Martin Skacan, Jan Korenek:
Towards hardware architecture for memory efficient IPv4/IPv6 Lookup in 100 Gbps networks. 108-111 - Syed Saif Abrar, Maksim Jenihhin
Extensible open-source framework for translating RTL VHDL IP cores to SystemC. 112-115 - Jiri Petrlik, Lukás Sekanina:
Multiobjective evolution of approximate multiple constant multipliers. 116-119 - Jan Kastil
Hardware architecture for the fast pattern matching. 120-123 - Gabriel Nagy, Daniel Arbet
Digital methods of offset compensation in 90nm CMOS operational amplifiers. 124-127 - Simona Buchovecká, Josef Hlavác:
Frequency injection attack on a random number generator. 128-130 - Pavel Fiala
Embedded microcontroller system for PilsenCUBE picosatellite. 131-134 - Amir Hasanbegovic, Snorre Aunet:
Proton beam characterization at Oslo Cyclotron Laboratory for radiation testing of electronic devices. 135-140 - Mojtaba Valinataj
Enhanced fault-tolerant Network-on-Chip architecture using hierarchical agents. 141-146 - Julien Saade, Frédéric Pétrot, Andre Picco, Joel Huloux, Abdelaziz Goulahsen:
A system-level overview and comparison of three High-Speed Serial Links: USB 3.0, PCI Express 2.0 and LLI 1.0. 147-152 - Syed Rameez Naqvi, Robert Najvirt, Andreas Steininger
A Multi-Credit Flow Control scheme for asynchronous NoCs. 153-158 - Muhammad Aamir Khan, Hans G. Kerkhoff:
An indirect technique for estimating reliability of analog and mixed-signal systems during operational life. 159-164 - Krzysztof Siwiec
Intermediate frequency filter calibration method for radio frequency receivers in modern CMOS technologies. 165-169 - Juraj Brenkus, Viera Stopjaková
Numerical method for DC fault analysis simplification and simulation time reduction. 170-174 - Tomas Drahonovsky, Martin Rozkovec
Relocation of reconfigurable modules on Xilinx FPGA. 175-180 - Petr Pfeifer
On performance estimation of a scalable VLIW soft-core in XILINX FPGAs. 181-186 - Tobias Koal, Markus Ulbricht, Piet Engelke, Heinrich Theodor Vierhaus:
On the feasibility of combining on-line-test and self repair for logic circuits. 187-192 - Hans Kristian Otnes Berge, Snorre Aunet:
Yield-oriented energy and performance model for subthreshold circuits with Vth variations. 193-198 - Dominik Kasprowicz
VeSFET as an analog-circuit component. 199-204 - Srijan Kumar, Sudip Roy, Partha Pratim Chakrabarti, Bhargab B. Bhattacharya, Krishnendu Chakrabarty
Efficient mixture preparation on digital microfluidic biochips. 205-210 - Jaroslav Sykora:
Composing data-driven circuits using handshake in the clock-synchronous domain. 211-214 - Hiroshi Yamazaki, Motohiro Wakazono, Toshinori Hosokawa, Masayoshi Yoshimura:
A don't care identification method for test compaction. 215-218 - Martin Chloupek, Jiri Jenícek, Ondrej Novák, Martin Rozkovec
Test pattern decompression in parallel scan chain architecture. 219-223 - Hong-Yi Huang, Chinet Otic Mocorro, Julyver Pinaso, Kuo-Hsing Cheng:
Indoor energy harvesting using photovoltaic cell for battery recharging. 224-227 - Jørgen Andreas Michaelsen, Dag T. Wisland:
Noise and linearity analysis of a frequency to voltage converter. 228-231 - Paul Ehrlich, Stephan Radke:
Energy-aware software development for embedded systems in HW/SW co-design. 232-235 - Hong-Yi Huang, Cheng-Yu Chen, Kuo-Hsing Cheng:
External capacitorless low dropout linear regulator using cascode structure. 236-239 - Johannes Seiter, Michael Hofbauer
FPGA based time-of-flight 3D camera characterization system. 240-245 - Anna Bernasconi
Error resilient OBDDs. 246-249 - Hsuan-Ling Kao
Design of an S-band 0.35 µm AlGaN/GaN LNA using cascode topology. 250-253 - Bahram N. Uchevler, Kjetil Svarstad
Assertion based verification using PSL-like properties in Haskell. 254-257 - Bahareh J. Farahani
Reliability-aware cross-layer custom instruction screening. 258-262 - Daniel Arbet
Efficiency of oscillation-based BIST in 90nm CMOS active analog filters. 263-266 - Ondrej Hnilicka:
FPGA architecture for fast floating point matrix inversion using uni-dimensional systolic array based structure. 267-270 - Stefan Kristofík
Redundancy algorithm for embedded memories with block-based architecture. 271-274 - Marcela Simková, Zdenek Kotásek, Cristiana Bolchini
Analysis and comparison of functional verification and ATPG for testing design reliability. 275-278 - Vladimir Petrovic, Zoran Stamenkovic
Fault-Tolerant Reconfigurable Low-Power pseudoRandom number Generator. 279-282 - Egor S. Sogomonyan, Stefan Weidling, Michael Gössel:
A new method for correcting time and soft errors in combinational circuits. 283-286 - Andrej Kincel, Marcel Baláz:
MBIST for LEON3 processor core cache. 287-288 - Karel Szurman, Jan Kastil
Fault tolerant CAN bus control system implemented into FPGA. 289-292 - Martin Pospisilik, Petr Neumann:
Improved design of the uninterruptable power supply unit for powering of network devices. 293-294 - Mohamed A. Wanas, Mohamed A. Abd El-Ghany
Hybrid Mesh-Ring wireless NoC for multi-core system. 295-296 - Tomas Napravnik, Premysl Ziska, Jiri Jakovenko
Novel model calibration method based on differential evolution used for SCR model fitting. 297-298
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