default search action
CODES+ISSS 2016: Pittsburgh, Pennsylvania, USA
- Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES 2016, Pittsburgh, Pennsylvania, USA, October 1-7, 2016. ACM 2016, ISBN 978-1-4503-4483-8
- Venkateshwar Kottapalli, Sunil P. Khatri:
A practical methodology to validate the statistical behavior of bloom filters. 1:1-1:8 - Yuankun Xue, Paul Bogdan:
Scalable and realistic benchmark synthesis for efficient NoC performance evaluation: a complex network analysis approach. 2:1-2:10 - Chi-Kang Chen, Hsin-I Wu, Chi-Ting Hsiao, Ren-Song Tsay:
An accurate and flexible early memory system power evaluation approach using a microcomponent method. 3:1-3:8 - Aviral Shrivastava
, Patricia Derler
Time in cyber-physical systems. 4:1-4:10 - Jie Guo, Chuhan Min, Tao Cai, Yiran Chen:
A design to reduce write amplification in object-based NAND flash devices. 5:1-5:10 - Hsin-Yu Chang, Chien-Chung Ho, Yuan-Hao Chang
How to enable software isolation and boost system performance with sub-block erase over 3D flash memory. 6:1-6:10 - Yu-Ming Chang, Yung-Chun Li, Ping-Hsien Lin, Hsiang-Pang Li, Yuan-Hao Chang
Realizing erase-free SLC flash memory with rewritable programming design. 7:1-7:10 - Farzad Samie, Lars Bauer, Jörg Henkel:
IoT technologies for embedded computing: a survey. 8:1-8:10 - Farzad Samie, Vasileios Tsoutsouras, Sotirios Xydis, Lars Bauer, Dimitrios Soudris
Distributed QoS management for internet of things under resource constraints. 9:1-9:10 - Nima Karimian, Paul A. Wortman, Fatemeh Tehranipoor:
Evolving authentication design considerations for the internet of biometric things (IoBT). 10:1-10:10 - Ehsan Saboori
Fast and cycle-accurate simulation of multi-threaded applications on SMP architectures using hybrid prototyping. 11:1-11:10 - Dandan Li, Senzhang Wang, Shuzhen Yao, Yuhang Liu, Yuanqi Cheng, Xian-He Sun:
Efficient design space exploration by knowledge transfer. 12:1-12:10 - Weiwen Jiang, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Xianzhang Chen
Optimal functional-unit assignment and buffer placement for probabilistic pipelines. 13:1-13:10 - Ke Wang, Kevin Angstadt, Chunkun Bo, Nathan Brunelle, Elaheh Sadredini
An overview of micron's automata processor. 14:1-14:3 - Marco Minutoli
Enabling the high level synthesis of data analytics accelerators. 15:1-15:3 - Katayoun Neshatpour, Avesta Sasan, Houman Homayoun:
Big data analytics on heterogeneous accelerator architectures. 16:1-16:3 - Bita Darvish Rouhani, Azalia Mirhoseini, Farinaz Koushanfar
Going deeper than deep learning for massive data analytics under physical constraints. 17:1-17:3 - Petra R. Maier, Veit Kleeberger
Fault injection at host-compiled level with static fault set reduction for SoC firmware robustness testing. 18:1-18:10 - Junshi Wang, Letian Huang, Qiang Li, Guangjun Li, Axel Jantsch
Optimizing the location of ECC protection in network-on-chip. 19:1-19:10 - Hung-Sheng Chang, Yuan-Hao Chang
A disturbance-aware sub-block design to improve reliability of 3D MLC flash memory. 20:1-20:10 - Mischa Möstl
Self-aware systems for the internet-of-things. 21:1-21:9 - Mimi Xie, Mengying Zhao, Chen Pan, Hehe Li, Yongpan Liu, Youtao Zhang, Chun Jason Xue, Jingtong Hu
Checkpoint aware hybrid cache architecture for NV processor in energy harvesting powered systems. 22:1-22:10 - Rubén Braojos, David Atienza, Mohamed M. Sabry Aly, Tony F. Wu, H.-S. Philip Wong, Subhasish Mitra, Giovanni Ansaloni:
Nano-engineered architectures for ultra-low power wireless body sensor nodes. 23:1-23:10 - Ishan G. Thakkar, Sai Vineel Reddy Chittamuru
Mitigation of homodyne crosstalk noise in silicon photonic NoC architectures with tunable decoupling. 24:1-24:10 - Paul Bogdan, Miroslav Pajic
Making the internet-of-things a reality: from smart models, sensing and actuation to energy-efficient architectures. 25:1-25:10 - Nadja Peters, Sangyoung Park
Web browser workload characterization for power management on HMP platforms. 26:1-26:10 - Bryan Donyanavard, Tiago Mück, Santanu Sarma, Nikil D. Dutt
SPARTA: runtime task allocation for energy efficient heterogeneous many-cores. 27:1-27:10 - Jelena Spasic, Di Liu, Todor P. Stefanov
Energy-efficient mapping of real-time applications on heterogeneous MPSoCs using task replication. 28:1-28:10 - Arquimedes Canedo:
Industrial IoT lifecycle via digital twins. 29:1 - Hsinchung Chen, Mohammad Abdullah Al Faruque
Security and privacy challenges in IoT-based machine-to-machine collaborative scenarios. 30:1-30:2 - Alexandra M. Porter, Md Muztoba, Ümit Y. Ogras
Human-machine communication for assistive IoT technologies. 31:1-31:2 - Shu-han Cheng, Guangyan Zhang, Jiwu Shu, Weimin Zheng:
AsyncStripe: I/O efficient asynchronous graph computing on a single server. 32:1-32:10 - Hyunsun Park, Dongyoung Kim, Junwhan Ahn, Sungjoo Yoo:
Zero and data reuse-aware fast convolution for deep neural networks on GPU. 33:1-33:10 - Hokchhay Tann, Soheil Hashemi, R. Iris Bahar
Runtime configurable deep neural networks for energy-accuracy trade-off. 34:1-34:10 - Peter R. Lewis
Types of computational self-awareness and how we might implement them. 35:1-35:2 - Marco Platzner
On-the-fly computing: self-aware heterogeneous multi-cores. 36:1-36:2 - Nikil D. Dutt
Conquering MPSoC complexity with principles of a self-aware information processing factory. 37:1-37:4
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-15 19:20 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: