default search action
CICC 1999: San Diego, CA, USA
- Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, CICC 1999, San Diego, CA, USA, May 16-19, 1999. IEEE 1999, ISBN 0-7803-5443-5
- Jess Chen, Dan Feng, Joel R. Phillips, Kenneth S. Kundert:
Simulation and modeling of intermodulation distortion in communication circuits. 5-8 - Akio Ushida, Yoshihiro Yamagami, Yoshifumi Nishio, Masayuki Takahashi, Kimihiro Ogawa:
Intermodulation analysis of mixer circuits based on frequency domain relaxation method. 9-12 - Ognen J. Nastov, Jacob K. White:
Grid selection strategies for time-mapped harmonic balance simulation of circuits with rapid transitions. 13-16 - Jaijeet Roychowdhury:
Automated macromodelling of "nonlinear" wireless blocks. 17-20 - Iason Vassiliou, Alberto L. Sangiovanni-Vincentelli:
A frequency-domain, Volterra series-based behavioral simulation tool for RF systems. 21-24 - R. Burger, G. Cesana, Maurizio Paolini, Maura Turolla, S. Vercelli:
A fully synthesizable parameterized Viterbi decoder. 27-30 - Mauro Chinosi, Roberto Zafalon, Carlo Guardiani:
Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioning. 31-34 - Ilhami Tomnoglu, Edoardo Charbon:
Watermarking-based copyright protection of sequential functions. 35-38 - Azra Rashid, Jeet Asher, William H. Mangione-Smith, Miodrag Potkonjak:
Hierarchical watermarking for protection of DSP filter cores. 39-42 - Ken W. K. Au, Trina M. Mann:
Multi-project management in real time. 45-52 - Sunsil Sinha, Mahesh Mehendale:
Integrated IC design approach based on software engineering paradigm. 53-56 - H. Peter Hofstee, Kevin J. Nowka
:
Beyond 1 GHz. 57-61 - Bart Vanhoof, Mercedes Peón, Gauthier Lafruit, Jan Bormans, Marc Engels, Ivo Bolsens:
A scalable architecture for MPEG-4 embedded zero tree coding. 65-68 - Shun-ichi Kurohmaru, Masatoshi Matsuo, Hiromasa Nakajima, Y. Kohashi, Tomonori Yonezawa, Toshihiro Mori-iwa, Masahiro Ohashi, M. Toujima, Tsuyoshi Nakamura, Mana Hamada, Takashi Hashimoto, H. Fujimoto, Yasuo Iizuka, Junji Michiyama, H. Komori:
A MPEG4 programmable codec DSP with an embedded pre/post-processing engine. 69-72 - Yukitoshi Tsuboi, Hideo Arai, Masaru Takahashi, Masuo Oku:
A low-power single-chip MPEG-2 CODEC LSI. 73-76 - T. Fujihira, H. Ohtsubo, H. Sakurai, K. Ohi:
Embedding DRAM in single chip MPEG1 codec LSI. 77-80 - Ann Marie Rincon, William R. Lee, Michael Slattery:
The changing landscape of system-on-a-chip design. 83-90 - G. Bollano, S. Claretto, L. Licciardi, Archille Montanaro, L. Pilati, Maura Turolla:
Intellectual property re-use and system emulation the keys to succeed the SoC challenge: a digital TV application. 91-94 - Satoshi Kumaki, Tetsuya Matsumura, Kamya Ishihara, Hiroshi Segawa, Kiyofumi Kawamoto, Hideo Ohira, Toshiaki Shimada, Hidenori Sato, Takashi Hattori, Tetsuro Wada, Hiroshi Honma, Tetsuya Watanabe, Hisakazu Sato, Ken'ichi Asano, Toyohiko Yoshida:
A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores. 95-98 - Geoffrey B. Jackson, Saleel V. Awsare, Lawrence D. Engh, Peter Holzmann, Oliver C. Kao, Carl R. Palmer, Aditya Raina:
An analog record, playback and processing system on a chip for mobile communications devices. 99-102 - Kang Lee, Benjamin Ng, Andrew Wang, Ray Kuhn, Derrick Johnson, Ross Kohler:
Single GSM mixed signal superchip with 96k bytes FLASH and low power micro-controller. 103-106 - H. Scott Fetterman, David G. Martin, David A. Rich:
CMOS pipelined ADC employing dither to improve linearity. 109-112 - Iuri Mehr, Larry Singer:
A 55-mW, 10-bit, 10 Msample/s Nyquist rate CMOS ADC. 113-116 - Yun-Ti Wang, Behzad Razavi:
An 8-bit 150-MHz CMOS A/D converter. 117-120 - Eric Fogleman, Ian Galton, William Huff, Henrik Jensen:
A 3.3 V single-poly CMOS audio ADC delta-sigma modulator with 98 dB peak SINAD. 121-124 - Russell E. Radke, Aria Eshraghi, Terri S. Fiez:
A spurious-free delta-sigma DAC using rotated data weighted averaging. 125-128 - Vittorio Comino, Allen C. Lu:
A bandpass sigma-delta modulator IC with digital branch-mismatch correction. 129-132 - Angelo Nagari, Alessandro Mecchia, Ermes Viani, Sergio Pernici, Pierangelo Confalonieri, Germano Nicollini:
A 2.7 V 11.8 mW baseband ADC with 72 dB dynamic range for GSM applications. 133-136 - Albert Z. Wang, Chen-Hui Tsay:
A low-triggering circuitry for dual-direction ESD protection. 139-142 - Ming-Dou Ker, Wen-Yu Lo, Chung-Yu Wu:
New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's. 143-146 - Arthur T. Bradley, Richard C. Jaeger, Jeffrey C. Suhling, Y. Zou:
Test chips for die stress characterization using arrays of CMOS sensors. 147-150 - Bapiraju Vinnakota, Ramesh Harjani:
Digital detection of parametric faults in data converters. 151-154 - Yavuz Kiliç, Mark Zwolinski
Testing analog circuits by supply voltage variation and supply current monitoring. 155-158 - Yiorgos Makris, Jamison Collins, Alex Orailoglu, Praveen Vishakantaiah:
TRANSPARENT: a system for RTL testability analysis, DFT guidance and hierarchical test generation. 159-162 - Bryon Moyer:
Simplifying in-system programming: evolving standards for ISP. 165-170 - Yaughn Betz, Jonathain Rose:
Circuit design, transistor sizing and wire layout of FPGA interconnect. 171-174 - Richard Cliff, Srinivas Reddy, Cameron McClintock, David Jefferslon, Christopher Lane, Ketan Zaveri, Manuel Mejia, Andy Lee, Ninh Ngo, Risa Altaf, Bruce Pedersen, Frank Heile, Jay Schleicher, John Turner:
A next generation architecture optimized for high density system level integration. 175-178 - Paul T. Sasaki, Yogendra Bobra, Warren E. Cory, Atul V. Cihia, Suresh M, Menon, Madhavi Kola, Mammen Thomas, Prasad Rau, Arch Zaliznyak:
A fast, predictable FPGA with PLLs, dual port SRAMs and active repeaters. 179-182 - William B. Andrew, Glenn Carl, Ravi K. Charath, James F. Hoff, Ron Modo, Hung Nguyen, William Smith, David Rhein, Joe Schulingkamp, Carolyn W. Spivak, James P. Steward, Akila Subramaniam:
A field programmable system chip which combines FPGA and ASIC circuitry. 183-186 - Brad Vest, Gwen Liang, Mark Chan, Eric Chun, Mark Fiester, Weiying Ding, Edmond Lau, Guu Lin, Behzad Nouban, Dirk Reese, Mian Smith, Nghia Tran, Stephanie Wong, Michael Woo, Myron Wong, John Costello:
A 4.9 ns, 3.3 volt, 512 macrocell, CMOS PLD with hot socket protection and fast in system programming. 187-190 - Simon D. Haynes, Antonio B. Ferrari, Peter Y. K. Cheung:
Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs. 191-194 - Behzad Razavi:
RF transmitter architectures and circuits. 197-204 - Mark Cloutier, Theodore Varelas, Christian Cojocaru, Florinel Balteanu
A 4-dB NF GPS receiver front-end with AGC and 2-b A/D. 205-208 - Joop P. M. Van Lammeren, Roy W. B. Wissing:
Mixed-signal quadrature demodulator with a multi-carrier regeneration system. 209-212 - Hooman Darabi, Asad A. Abidi:
An ultralow power single-chip CMOS 900 MHz receiver for wireless paging. 213-216 - Jean-Olivier Plouchart, Herschel A. Ainspan, Mehmet Soyuer:
A 5.2 GHz 3.3 V I/Q SiGe RF transceiver. 217-220 - David Rowe, Bret Pollack, James Pulver, W. Chon, Preston Jett, Larry W. Fullerton, Lawrence Larson:
A Si/SiGe HBT timing generator IC for high-bandwidth impulse radio applications. 221-224 - Michael Wood, George Smith, John Pennings:
Converting an SRAM from bulk Si to partially depleted SOI. 227-230 - Dong-Sun Min, Dietrich W. Langer:
Multiple twisted data line techniques for coupling noise reduction in embedded DRAMs. 231-234 - Steven Sullivan, Brad R. Johnson, Douglas Reid, Scott A. Taylor:
A 1.8 V, 2.0 ns cycle, 32 KB embedded memory with interleaved castout/reload. 235-238 - Jason Podaima, Glenn Gulak:
A self-timed, fully-parallel content addressable queue for switching applications. 239-242 - Tomonori Kataoka, Ikuo Fuchigami, Yoichi Nishida, Tomoo Kimura, Rie Aruga, Yasushi Okuda, Junji Michiyama:
A 1.4 V 60 MHz access, 0.25 μm embedded flash EEPROM. 243-246 - Marco Pasotti, Pier Luigi Rolandi, Roberto Canegallo, Danilo Gerna, Giovanni Guaitini, Frank Lhermet, Alan Kramer:
Analog sense amplifiers for high density NOR flash memories. 247-250 - Ayal Shoval, Omid Shoaei, Kathleen O. Lee, Robert H. Leonowich:
A CMOS mixed-signal 100 Mb/s receive architecture for fast Ethernet. 253-256 - Omit Shoaei, Ayal Shoval, Robert H. Leonowich:
A dual-speed 125 Mbaud/10 Mbaud CMOS transmitter for Fast Ethernet. 257-260 - Kamran Iravani, Farid Saleh, D. Lee, Patrick Fung, Paul Ta, Gary Miller:
Clock and data recovery for 1.25 Gb/s Ethernet transceiver in 0.35 μm CMOS. 261-264 - Lizhong Sun, Tad A. Kwasniewski:
A 1.25 GHz 0.35 μm monolithic CMOS PLL clock generator for data communications. 265-268 - Michael S. Kappes:
A 3 V-CMOS low distortion class AB line driver suitable for HDSL applications. 269-272 - Masaaki Soda, S. Shiori, Takenori Morikawa, M. Tachigori, I. Watanabe, Makoto Shibutani:
A 2.5-Gb/s one-chip receiver module for gigabit-to-the-home (GTTH) system. 273-276 - Anantha P. Chandrakasan, Raj Amirtharajah, Seong-Hwan Cho, James Goodman, Gangadhar Konduri, Joanna Kulik, W. Rabiner, Alice Wang:
Design considerations for distributed microsensor systems. 279-286 - Shyh-Yih Ma, Liang-Gee Chen:
A single chip CMOS APS camera with direct frame difference output. 287-290 - Minoru Fujishima, Yuji Kiniwa, Koichiro Hoh:
Band runlength coding for low-power continuous micro-monitors. 291-294 - Sanu hlathew, Ramalingam Sridhar:
A data-driven micropipeline structure using DSDCVSL. 295-298 - Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim:
A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells. 299-302 - Hee-Tae Ahn:
A ±25 ps jitter 1.9 V CMOS PLL for UltraSPARC microprocessor. 303-305 - Hemat Thapar, Sang-Soo Lee, Cormac Conroy, Richard Contreras, Alfred Yeung, Jenn-Gang Chern, Tzuwang Pan, Shih-Ming Shih:
Hard disk drive read channels: technology and trends. 309-316 - Marco Demicheli, Giacomino Bollati, Paolo Gadducci, L. Affortunati, Roberto Alini, G. Betti, I. Bietti, F. Brianti, Melchiorre Bruccoleri, M. Coltella, P. Demartini, Stefano Marchese, D. Ottini, Valerio Pisati, Salvatore Portaluri, A. Rossi, P. Savo, C. Tonci, Rinaldo Castello:
A 450 Mbit/s EPR4 PRML read/write channel. 317-320 - Xiaodong Wang, Richard R. Spencer:
A CMOS two-path tree search detector. 321-324 - Srinath Sridharan, L. Richard Carley:
A 110 MHz 350 mW 0.6μ CMOS 16-state generalized-target Viterbi detector for disk drive read channels. 325-328 - Michael P. Flynn, Michael Twohig, Raymond Byrne
A BiCMOS preamplifier/write-driver IC for tape drive. 329-332 - Stefano Marchese, Valerio Pisati, S. Portaluri, A. Savo, G. Vai, Steffen Lehr, Volker Neiss, C. Buechler, F. Zucker:
A BiCMOS 1× to 5× combined analog frontend IC for DVD-ROM and movie players. 333-337 - Ghavam G. Shahidi, Atul Ajmera, Fariborz Assaderaghi, Ronald J. Bolam, Harold Hovel, Effendi Leobandung, Werner Rausch, Devendra Sadana, Dominic Schepis, Lawrence F. Wagner, Larry Wissel, Kun Wu, Bijan Davai:
Device and circuit design issues in SOI technology. 339-346 - Jeannie H. Panner, Thomas R. Bednar, Patrick H. Buffet, Douglas W. Kemerer, Douglas W. Stout, Paul S. Zuchowski:
The first copper ASICs: A 12M-gate technology. 347-350 - Wolfgang Winkler, Johannes Borngräber, Heide Erzgraeber, Ha. Erzgraber, Bernd Heinemann, Dieter Knoll, H. Jörg Osten, Michael Pierschel, Klaus Pressel, Peter Schley:
Wireless communication integrated circuits with CMOS-compatible SiGe HBT technology modules. 351-358 - Mikako Miyama, Shiro Kamohara, Mitsuru Hiraki, Kazunori Onozawa, Hisaaki Kunitomo:
Pre-silicon parameter generation methodology using BSIM3 for device/circuit concurrent design. 359-363 - S. V. Kishore, Glenn Chang, Georgios Asmanis, Chris Hull, Frederic Stubbe:
Substrate-induced high-frequency noise in deep sub-micron MOSFETs for RF applications. 365-368 - Tajinder Manku, Michael S. Obrecht, Yi Lin:
RF simulations and physics of the channel noise parameters within MOS transistors. 369-372 - Thomas H. Lee:
Oscillator phase noise: a tutorial. 373-380 - Mihai A. Margarit, Joo Leong Tham, M. Jamal Deen
Noise analysis of a VCO with automatic amplitude control. 381-384 - Alper Demir, Jaijeet Roychowdhury:
Modeling and simulation of noise in analog/mixed-signal communication systems. 385-393 - Pierre J. Bricaud:
IP reuse creation for system-on-a-chip design. 395-401 - Kei Suzuki, Kouji Ara, Kazuo Yano:
Ow/L: An interface description language for IP reuse. 403-406 - Olaf Heuser, Horst-Lothar Fiedler:
A new method for reuse-driven design of digital circuits. 407-410 - David Dignam, Ben Garlick, Ed Hutchins, Oren Rubinstein:
An integrated environment for configurable designs. 411-414 - Peter Schindler, Klara Weidenbacher, Thomas Zimmermann:
IP repository, a Web based IP reuse infrastructure. 415-418 - Sandy Taylor:
The challenge of designing global signals in UDSM CMOS. 429-435 - Syed Zakir Hussain, Steften Rochel, David Overhauser, Resve Saleh:
Clock verification in the presence of IR-drop in the power distribution network. 437-440 - Payman Zarkesh-Ha, Tony Mule, James D. Meindl:
Characterization and modeling of clock skew with process variations. 441-444 - Byron Krauter, Sharad Mehrotra, V. Chandramouli:
Including inductive effects in interconnect timing analysis. 445-452 - Kenneth L. Shepard, Zhong Tian:
Return-limited inductances: a practical approach to on-chip inductance extraction. 453-456 - Lei He, Norman Chang, Shen Lin, O. Sam Nakagawa:
An efficient inductance modeling for on-chip interconnects. 457-460 - Arani Sinha, Salim Chowdhury:
Mesh-structured on-chip power/ground: design for minimum inductance and characterization for fast R, L extraction. 461-465 - Patrik Larsson:
Power supply noise in future IC's: a crystal ball reading. 467-474 - Akio Koyama, Masatoshi Tsuge, Jun'ya Kudo, Tatsuhiro Aida, Makio Uchida:
Switching well noise analysis and minimization strategy for low Vth CMOS integrated circuits. 475-478 - John P. Z. Lee, Frank Wang, Abhijit Phanse, Linda C. Smith:
Substrate cross talk noise characterization and prevention in 0.35 mμm CMOS technology. 479-482 - J. Briaire, K. S. Krisch:
Substrate injection and crosstalk in CMOS circuits. 483-486 - Ranjit Gharpurey:
A methodology for measurement and characterization of substrate noise in high frequency circuits. 487-490 - Raminderpal Singh:
A review of substrate coupling issues and modeling strategies. 491-499 - Farbod Behbahani, Weeguan Tan, Ali Karimi-Sanjaani, Andreas Roithmeier, Asad A. Abidi:
A wideband tunable CMOS channel-select filter for a low-IF wireless receiver. 501-504 - Dominique Python, Alain-Serge Porret, Christian C. Enz:
A 1 V 5th-order Bessel filter dedicated to digital standard processes. 505-508 - Tetsuro Itakura, Takashi Ueno, Hiroshi Tanimoto, Tadashi Arai:
A 2 Vpp linear input-range fully balanced CMOS transconductor and its application to a 2.5 V 2.5 MHz Gm-C LPF. 509-512 - Sunderarajan S. Mohan, Thomas H. Lee:
A 2.125 Gbaud 1.6 kΩ transimpedance preamplifier in 0.5 μm CMOS. 513-516 - Hamid R. Rategh, Hirad Samavati, Thomas H. Lee:
A 5 GHz, 1 mW CMOS voltage controlled differential injection locked frequency divider. 517-520 - Thaddeus Gabara:
A 3.25 Gb/s injection locked CMOS clock recovery cell. 521-524 - Mika Tiilikainen:
A novel high precision adjustment method for the transconductance of a MOSFET. 525-529 - Bryan Ackland, Paul D'Arcy:
A new generation of DSP architectures. 531-536 - Bryan D. Ackland, A. Anesko, D. Brinthaupt, S. J. Daubert, Asawaree Kalavade, J. Knobloch, E. Micca, M. Moturi, Chris J. Nicol, Jay H. O'Neill, Joe Othmer, Eduard Sackinger, Kanwar Jit Singh, J. Sweet, C. J. Terman, Joseph Williams:
A single-chip 1.6 billion 16-b MAC/s multiprocessor DSP. 537-540 - Tod Wolf:
A DSP Reed-Solomon coder. 541-544 - Ji-Ning Duan, Li-Jen Ko, Babak Daneshrad:
Versatile beamforming ASIC architecture for broadband fixed wireless access. 545-548 - Paul T. Capozza, Brian J. Holland, Thomas M. Hopkinson, Roberto L. Landrau:
A single-chip narrowband frequency domain excisor for a Global Positioning System (GPS) receiver. 549-552 - Silas Li, David Lewis:
470 MHz digital filter on delta-sigma modulated signals. 553-556 - Arindam Mukherjee, Malgorzata Marek-Sadowska, Stephen I. Long:
Wave pipelining YADDs-a feasibility study. 559-562 - Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai:
Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs. 563-566 - Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums:
ANACONDA: robust synthesis of analog circuits via stochastic pattern search. 567-570 - Yhonkyong Choi, Chong S. Rim:
Circuit partitioning by quadratic Boolean programming for reconfigurable circuit boards. 571-574 - Makoto Nagata
Measurements and analyses of substrate noise waveform in mixed signal IC environment. 575-578 - M. Klemme, Erich Barke:
An extended bipolar transistor model for substrate crosstalk analysis. 579-582 - Suet Fong Tin, Kartikeya Mayaram:
Substrate network modeling for CMOS RF circuit simulation. 583-586 - Hiroshi Suzuki, Yun-Nan Chang, Keshab K. Parhi
Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systems. 589-592 - Abdellatif Bellaouar, Michael S. Obrecht, Amr M. Fahim, Mohamed I. Elmasry:
A low-power direct digital frequency synthesizer architecture for wireless communications. 593-596 - W.-H. Chang, D. R. Pehlke, R. Yu:
A low-power and low-noise CMOS prescaler for 900 MHz to 1.9 GHz wireless applications. 597-600 - Hormoz Djahanshahi, Flemming Hansen, C. André T. Salama:
Giga bit per second per pin differential CMOS circuits for pseudo ECL signaling. 601-604 - Poki Chen, Shen-Iuan Liu:
A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution. 605-608 - Regan Zane, Dragan Maksimovic:
Frequency scalable non-linear waveform generator for mixed-signal power-factor-correction IC controller. 609-612 - Abdelaziz Benachour, Sherif H. K. Embabi, Akbar Ali:
A 1.5 GHz, sub-2 mW CMOS dual-modulus prescaler. 613-616 - Howard Sachs, Mark Birnbaum:
VSIA technical challenges. 619-622 - Bill Cordan:
An efficient bus architecture for system-on-chip design. 623-626 - Steven Winegarden:
A bus architecture centric configurable processor system. 627-630 - Peter M. Nyasulu, Ralph Mason, W. Martin Snelgrove, Duncan G. Elliott:
Minimizing the effect of the host bus on the performance of a computational RAM logic-in-memory parallel-processing system. 631-634 - Jacobo Riesco, Juan Carlos Diaz, Pierre Plaza:
The μPP ASIC: design, methodologies and tools for a pay phone system-on-a-chip based on an ARM core and design reuse. 635-638 - Alain-Serge Porret, Thierry Melly, Christian C. Enz:
Design of high-Q varactors for low-power wireless applications using a standard CMOS process. 641-644 - Francesco Svelto, Stefano Deantoni, Rinaldo Castello:
A 1.3 GHz CMOS VCO with 28% frequency tuning. 645-648 - Dirk Pfaff, Qiuting Huang:
A quarter-micron CMOS, 1 GHz VCO/prescaler-set for very low power applications. 649-652 - Amr N. Hafez, Mohamed I. Elmasry:
Fully integrated low phase-noise PLLs using closed-loop voltage-to-frequency converter architectures. 653-656 - Jeffrey Harrison, Neil Weste:
A wideband quadrature LO generator in digital CMOS. 657-659 - Brian A. Floyd
A 900-MHz, 0.8-μm CMOS low noise amplifier with 1.2-dB noise figure. 661-664 - John R. Long, Michael C. Maliepaard:
A 1 V 900 MHz image-reject downconverter in 0.5 μm CMOS. 665-668
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-28 20:17 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: