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CASES 2002: Grenoble, France
- Shuvra S. Bhattacharyya, Trevor N. Mudge, Wayne H. Wolf, Ahmed Amine Jerraya:
Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002. ACM 2002, ISBN 1-58113-575-0
Embedded System Techniques
- Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg:
A case for dynamic pipeline scaling. 1-8 - Jack Liu, Fred C. Chow:
A near-optimal instruction scheduler for a tightly constrained, variable instruction set embedded processor. 9-18 - Thomas Genssler, Alexander Christoph, Michael Winter, Oscar Nierstrasz
, Stéphane Ducasse, Roel Wuyts
Components for embedded software: the PECOS approach. 19-26 - Dirk Fischer, Jürgen Teich, Michael Thies, Ralph Weper:
Efficient architecture/compiler co-exploration for ASIPs. 27-34
Architecture Adaptation and Synthesis
- Mukund Sivaraman, Shail Aditya:
Cycle-time aware architecture synthesis of custom hardware accelerators. 35-42 - Mladen Nikitovic, Mats Brorsson:
An adaptive chip-multiprocessor architecture for future mobile terminals. 43-49 - Amol Bakshi, Jingzhao Ou, Viktor K. Prasanna:
Towards automatic synthesis of a class of application-specific sensor networks. 50-58
Extention and Benchmarks
- Michael Ward, Neil C. Audsley:
Hardware implementation of the Ravenscar Ada tasking profile. 59-68 - Bengu Li, Rajiv Gupta
Bit section instruction set extension of ARM for embedded applications. 69-78 - Hillery C. Hunter, Wen-mei W. Hwu:
Code coverage and input variability: effects on architecture and compiler research. 79-87
Power in Memory and Network Processors
- Jayaprakash Pisharath, Alok N. Choudhary:
An integrated approach to reducing power dissipation in memory hierarchies. 88-97 - Afzal Malik, Bill Moyer, Roger Zhou:
Embedded cache architecture with programmable write buffer support for power and performance flexibility. 98-107 - Gokhan Memik, William H. Mangione-Smith:
Increasing power efficiency of multi-core network processors through data filtering. 108-116
Program Transformation
- Esther Salamí
Cost effective memory disambiguation for multimedia codes. 117-126 - Mahmut T. Kandemir, Ismail Kadayif, Alok N. Choudhary, Joseph Zambreno:
Optimizing inter-nest data locality. 127-135 - Tao Zhang, Santosh Pande
Leakage-proof program partitioning. 136-145
Scheduling and Frequency Scaling for Power
- Jian-Liang Kuo, Tien-Fu Chen:
Dynamic voltage leveling scheduling for real-time embedded systems on low-power variable speed processors. 147-155 - Zhijian Lu, Jason Hein, Marty Humphrey, Mircea R. Stan
Control-theoretic dynamic frequency and voltage scaling for multimedia workloads. 156-163 - Ravindra Jejurikar, Rajesh K. Gupta:
Energy aware task scheduling with task synchronization for embedded real time systems. 164-169
Compilers and Program Analysis
- Jeffry T. Russell, Margarida F. Jacome:
Scenario-based software characterization as a contingency to traditional program profiling. 170-177 - Jinhwan Kim, Sungjoon Jung, Yunheung Paek, Gang-Ryung Uh:
Experience with a retargetable compiler for a commercial network processor. 178-187 - Alex K. Jones
PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. 188-197
Embedded System Techniques
- Jiang Xu, Wayne H. Wolf:
Wave pipelining for application-specific networks-on-chips. 198-201 - Stephen W. Melvin, Yale N. Patt:
Handling of packet dependencies: a critical issue for highly parallel network processors. 202-209 - Hongbo Yang, Guang R. Gao, Clement Leung:
On achieving balanced power consumption in software pipelined loops. 210-217 - Franco Gatti, Andrea Acquaviva, Luca Benini, Bruno Riccò:
Low Power Control Techniques For TFT LCD Displays. 218-224
Power and Battery Management
- Sung I. Park, Mani B. Srivastava:
Dynamic battery state aware approaches for improving battery utilization. 225-231 - Davide Bruni, Luca Benini, Bruno Riccò:
System lifetime extension by battery management: an experimental work. 232-237 - Andreas Weissel, Frank Bellosa:
Process cruise control: event-driven clock scaling for dynamic power management. 238-246
System Synthesis
- Karim Ben Chehida, Michel Auguin:
HW / SW partitioning approach for reconfigurable system design. 247-251 - Manoj Kumar Jain
An efficient technique for exploring register file size in ASIP synthesis. 252-261 - Philip Brisk
Instruction generation and regularity extraction for reconfigurable processors. 262-269
Software Transformation
- Daniel Ménard, Daniel Chillet
Automatic floating-point to fixed-point conversion for DSP code generation. 270-276 - Dae-Hwan Kim
Iterative procedural abstraction for code size reduction. 277-279 - Raya Leviathan, Amir Pnueli:
Validating software pipelining optimizations. 280-287
Embedded Programs
- Sumant Kowshik, Dinakar Dhurjati, Vikram S. Adve:
Ensuring code safety without runtime checks for real-time control systems. 288-297 - Alwyn Goodloe, Michael McDougall, Carl A. Gunter, Rajeev Alur:
Predictable programs in barcodes. 298-303 - Anders Nilsson, Torbjörn Ekman, Klas Nilsson:
Real Java for real time - gain and pain. 304-311
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