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25th ASP-DAC 2020: Beijing, China
- 25th Asia and South Pacific Design Automation Conference, ASP-DAC 2020, Beijing, China, January 13-16, 2020. IEEE 2020, ISBN 978-1-7281-4123-7
- Lin Cheng, Xinyuan Ge, Wai Chiu Ng, Wing-Hung Ki
, Jiawei Zheng, Tsz Fai Kwok, Chi-Ying Tsui, Ming Liu:
Design of a Single-Stage Wireless Charger with 92.3%-Peak-Efficiency for Portable Devices Applications. 1-2 - Sujin Park, Geon-Hwi Lee, Seungmin Oh, SeongHwan Cho:
A Capacitance-to-Digital Converter with Differential Bondwire Accelerometer, On-chip Air Pressure and Humidity Sensor in 0.18 μm CMOS. 3-4 - Zheng Li, Jian Pang, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You
A 28GHz CMOS Differential Bi-Directional Amplifier for 5G NR. 5-6 - Ching-Hwa Cheng:
A Quantity Evaluation and Reconfiguration Mechanism for Signal- and Power-Interconnections in 3D-Stacking System. 7-8 - Junichiro Kadomoto, Satoshi Mitsuno, Hidetsugu Irie, Shuichi Sakai
An Inductively Coupled Wireless Bus for Chiplet-Based Systems. 9-10 - Kento Hasegawa, Ryota Ishikawa, Makoto Nishizawa, Kazushi Kawamura, Masashi Tawada, Nozomu Togawa
FPGA-based Heterogeneous Solver for Three-Dimensional Routing. 11-12 - Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen:
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network. 13-18 - Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza:
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. 19-25 - Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer
High-Definition Routing Congestion Prediction for Large-Scale FPGAs. 26-31 - Younggwang Jung, Daijoon Hyun, Youngsoo Shin:
Integrated Airgap Insertion and Layer Reassignment for Circuit Timing optimization. 32-37 - Shaobin Ma, Xiaoyi Wang, Sheldon X.-D. Tan, Liang Chen, Jian He:
An Adaptive Electromigration Assessment Algorithm for Full-chip Power/Ground Networks. 38-43 - Vidya A. Chhabria
Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques. 44-49 - Limin Wang
Analyzing The Security of The Cache Side Channel Defences With Attack Graphs. 50-55 - Wenjian He
iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPU. 56-61 - Jiaji He, Haocheng Ma, Xiaolong Guo, Yiqiang Zhao, Yier Jin
Design for EM Side-Channel Security through Quantitative Assessment of RTL Implementations. 62-67 - Victor M. van Santen
Impact of Self-Heating on Performance, Power and Reliability in FinFET Technology. 68-73 - Han Zhou, Shuyuan Yu, Zeyu Sun, Sheldon X.-D. Tan:
Reliable Power Grid Network Design Framework Considering EM Immortalities for Multi-Segment Wires. 74-79 - Uzair Sharif, Daniel Mueller-Gritschneder
Investigating the Inherent Soft Error Resilience of Embedded Applications by Full-System Simulation. 80-84 - Lei Yang, Weiwen Jiang, Weichen Liu
Co-Exploring Neural Architecture and Network-on-Chip Design for Real-Time Artificial Intelligence. 85-90 - Dae Hee Kim, Rakesh Nagi
Thanos: High-Performance CPU-GPU Based Balanced Graph Partitioning Using Cross-Decomposition. 91-96 - Sidhartha Sankar Rout, Badri M, Sujay Deb:
Reutilization of Trace Buffers for Performance Enhancement of NoC based MPSoCs. 97-102 - Mathieu Jan, Mihail Asavoae, Martin Schoeberl
Formal Semantics of Predictable Pipelines: a Comparative Study. 103-108 - Mengchu Li, Tsun-Ming Tseng
Maximizing the Communication Parallelism for Wavelength-Routed Optical Networks-On-Chips. 109-114 - Stefan Hillmich
Concurrency in DD-based Quantum Circuit Simulation. 115-120 - Alwin Zulehner, Stefan Hillmich
Approximation of Quantum States Using Decision Diagrams. 121-126 - Lukas Burgholzer
Improved DD-based Equivalence Checking of Quantum Circuits. 127-132 - Sheng-Jung Yu, Chen-Chien Kao, Chia-Han Huang, Iris Hui-Ru Jiang:
Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability. 133-138 - Jeongwoo Heo, Kwangok Jeong, Taewhan Kim, Kyu-Myung Choi:
Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process Nodes. 139-144 - Chaofei Yang, Hai Li, Yiran Chen, Jiang Hu:
Enhancing Generalization of Wafer Defect Detection by Data Discrepancy-aware Preprocessing and Contrast-varied Augmentation. 145-150 - Hongfei Wang, Wenjie Cai, Jianwen Li, Kun He:
Exploring Graphical Models with Bayesian Learning and MCMC for Failure Diagnosis. 151-156 - Pengfei Qiu, Qian Wang, Dongsheng Wang, Yongqiang Lyu, Zhaojun Lu, Gang Qu:
Mitigating Adversarial Attacks for Deep Neural Networks by Input Deformation and Augmentation. 157-162 - Zheyu Yan, Yiyu Shi, Wang Liao, Masanori Hashimoto
When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies. 163-168 - Elbruz Ozen
Concurrent Monitoring of Operational Health in Neural Networks Through Balanced Output Partitions. 169-174 - Fan Chen, Linghao Song
PARC: A Processing-in-CAM Architecture for Genomic Long Read Pairwise Alignment using ReRAM. 175-180 - Shikhar Tuli, Marco Rios, Alexandre Levisse, David Atienza:
RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures. 181-186 - Fan Zhang
Defects Mitigation in Resistive Crossbars for Analog Vector Matrix Multiplication. 187-192 - Mingjie Liu, Wuxi Li, Keren Zhu
S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity. 193-198 - Niklas Kochdumper, Ahmad Tarraf
Establishing Reachset Conformance for the Formal Analysis of Analog Circuits. 199-204 - Peng Chen, Weichen Liu
Contention Minimized Bypassing in SMART NoC. 205-210 - Wenshuo Li, Xuefei Ning
FTT-NAS: Discovering Fault-Tolerant Neural Architecture. 211-216 - Sayandeep Sanyal, Aritra Hazra, Pallab Dasgupta, Scott Morrison, Sudhakar Surendran, Lakshmanan Balasubramanian:
The Notion of Cross Coverage in AMS Design Verification. 217-222 - Yangdi Lyu, Prabhat Mishra
Automated Test Generation for Activation of Assertions in RTL Models. 223-228 - Sheriff Sadiqbatcha, Yue Zhao, Jinwei Zhang, Hussam Amrouch
Machine Learning Based Online Full-Chip Heatmap Estimation. 229-234 - Chuliang Guo
A Reconfigurable Approximate Multiplier for Quantized CNN Applications. 235-240 - Noel Daniel Gundi, Tahmoures Shabanian, Prabal Basu, Pramesh Pandey, Sanghamitra Roy
EFFORT: Enhancing Energy Efficiency and Error Resilience of a Near-Threshold Tensor Processing Unit. 241-246 - Zhaohui Chen, Yuan Ma, Tianyu Chen, Jingqiang Lin, Jiwu Jing:
Towards Efficient Kyber on FPGAs: A Processor for Vector of Polynomials. 247-252 - Chiou-Yng Lee, Jiafeng Xie:
Efficient Subquadratic Space Complexity Digit-Serial Multipliers over GF(2m) based on Bivariate Polynomial Basis Representation. 253-258 - Pruthvy Yellu, Mohammad Mezanur Rahman Monjur, Timothy Kammerer, Dongpeng Xu
Security Threats and Countermeasures for Approximate Arithmetic Computing. 259-264 - Hemanta Kumar Mondal, Navonil Chatterjee, Rodrigo Cataldo, Jean-Philippe Diguet:
Broadcast Mechanism Based on Hybrid Wireless/Wired NoC for Efficient Barrier Synchronization in Parallel Computing. 265-270 - Mian Qin
A Generic FPGA Accelerator for Minimum Storage Regenerating Codes. 271-276 - Yen-Ting Chen
Parallel-Log-Single-Compaction-Tree: Flash-Friendly Two-Level Key-Value Management in KVSSDs. 277-282 - Jung-Woo Chang
Towards Design Methodology of Efficient Fast Algorithms for Accelerating Generative Adversarial Networks on FPGAs. 283-288 - Baoting Li, Longjun Liu
Designing Efficient Shortcut Architecture for Improving the Accuracy of Fully Quantized Neural Networks Accelerator. 289-294 - Maedeh Hemmat, Tejas Shah, Yuhua Chen, Joshua San Miguel
CRANIA: Unlocking Data and Value Reuse in Iterative Neural Network Architectures. 295-300 - Xiaolong Ma, Geng Yuan, Sheng Lin, Caiwen Ding, Fuxun Yu, Tao Liu, Wujie Wen, Xiang Chen, Yanzhi Wang:
Tiny but Accurate: A Pruned, Quantized and Optimized Memristor Crossbar Framework for Ultra Efficient DNN Implementation. 301-306 - Yi Wang
Towards Read-Intensive Key-Value Stores with Tidal Structure Based on LSM-Tree. 307-312 - Li Yang, Shaahin Angizi, Deliang Fan:
A Flexible Processing-in-Memory Accelerator for Dynamic Channel-Adaptive Deep Neural Networks. 313-318 - Reika Kinoshita, Chihiro Matsui, Atsuya Suzuki, Shouhei Fukuyama, Ken Takeuchi:
Workload-aware Data-eviction Self-adjusting System of Multi-SCM Storage to Resolve Trade-off between SCM Data-retention Error and Storage System Performance. 319-324 - Hanbo Sun, Zhenhua Zhu, Yi Cai, Xiaoming Chen, Yu Wang, Huazhong Yang:
An Energy-Efficient Quantized and Regularized Training Framework For Processing-In-Memory Accelerators. 325-330 - Chun-Han Chiang, Fu-Yu Chuang, Yao-Wen Chang:
Unified Redistribution Layer Routing for 2.5D IC Packages. 331-337 - Kevin E. Murray, Sheng Zhong, Vaughn Betz:
AIR: A Fast but Lazy Timing-Driven FPGA Router. 338-344 - Dongwon Park, Daeyeal Lee, Ilgweon Kang, Sicun Gao, Bill Lin, Chung-Kuan Cheng:
SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm. 345-350 - M. D. Arafat Kabir, Yarui Peng
Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools. 351-356 - Zhongqi Cheng, Emad Malekzadeh Arasteh, Rainer Dömer:
Event Delivery using Prediction for Faster Parallel SystemC Simulation. 357-362 - Gabriel Busnot, Tanguy Sassolas, Nicolas Ventroux, Matthieu Moy:
Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models. 363-368 - Alessandro Cornaglia, Md. Shakib Hasan, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel:
JIT-Based Context-Sensitive Timing Simulation for Efficient Platform Exploration. 369-374 - Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Towards Automatic Hardware Synthesis from Formal Specification to Implementation. 375-380 - Bin Gao:
Emerging Non-Volatile Memories for Computation-in-Memory. 381-384 - Jintao Yu
The Power of Computation-in-Memory Based on Memristive Devices. 385-392 - Christopher Münch, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Tolerating Retention Failures in Neuromorphic Fabric based on Emerging Resistive Memories. 393-400 - Kai Ni, Sourav Dutta, Suman Datta
Ferroelectrics: From Memory to Computing. 401-406 - Juejian Wu, Yixin Xu, Bowen Xue, Yu Wang, Yongpan Liu, Huazhong Yang, Xueqing Li:
Adaptive Circuit Approaches to Low-Power Multi-Level/Cell FeFET Memory. 407-413 - Minli Julie Liao, Jack Sampson:
Emerging memories as enablers for in-memory layout transformation acceleration and virtualization. 414-421 - Yandong Luo, Shimeng Yu
Benchmark Non-volatile and Volatile Memory Based Hybrid Precision Synapses for In-situ Deep Neural Network Training. 422-427 - Wenjian Yu, Ming Yang, Yao Feng, Ganqu Cui, Ben Gu:
Capacitance Extraction and Power Grid Analysis Using Statistical and AI Methods. 428-433 - Haoyu Yang, Wei Zhong, Yuzhe Ma
VLSI Mask Optimization: From Shallow To Deep Learning. 434-439 - Shuhan Zhang
Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits. 440-445 - Dennis D. Weller, Michael Hefenbrock, Mehdi Baradaran Tahoori, Jasmin Aghassi-Hagmann, Michael Beigl:
Programmable Neuromorphic Circuit based on Printed Electrolyte-Gated Transistors. 446-451 - Shasha Guo, Ziyang Kang, Lei Wang, Shiming Li, Weixia Xu:
HashHeat: An O(C) Complexity Hashing-based Filter for Dynamic Vision Sensor. 452-457 - Yuki Kume, Song Bian, Takashi Sato
A Tuning-Free Hardware Reservoir Based on MOSFET Crossbar Array for Practical Echo State Network Implementation. 458-463 - Qian Lou
MindReading: An Ultra-Low-Power Photonic Accelerator for EEG-based Human Intention Recognition. 464-469 - Zirui Xu, Fuxun Yu, Xiang Chen:
LanCe: A Comprehensive and Lightweight CNN Defense Methodology against Physical Adversarial Attacks on Embedded Multimedia Applications. 470-475 - Jiaqi Gu, Zheng Zhao, Chenghao Feng, Mingjie Liu, Ray T. Chen, David Z. Pan:
Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture. 476-481 - Yangdi Lyu, Prabhat Mishra
Automated Trigger Activation by Repeated Maximal Clique Sampling. 482-487 - Kuei-Huan Chang, Po-Hao Huang, Honggang Yu, Yier Jin
Audio Adversarial Examples Generation with Recurrent Neural Networks*. 488-493 - Xiaolong Ma, Zhe Li, Hongjia Li, Qiyuan An, Qinru Qiu, Wenyao Xu, Yanzhi Wang:
Database and Benchmark for Early-stage Malicious Activity Detection in 3D Printing. 494-499 - Sanjay Moulik
EA-HRT: An Energy-Aware scheduler for Heterogeneous Real-Time systems. 500-505 - Yujie Zhu, Xue Zhao, Keni Qiu:
Insights and Optimizations on IR-drop Induced Sneak-Path for RRAM Crossbar-based Convolutions. 506-511 - Shuo-Han Chen
Boosting the Profitability of NVRAM-based Storage Devices via the Concept of Dual-Chunking Data Deduplication. 512-517 - Shulin Zeng, Hanbo Sun, Yu Xing
Black Box Search Space Profiling for Accelerator-Aware Neural Architecture Search. 518-523 - Bosheng Liu
Search-free Accelerator for Sparse Convolutional Neural Networks. 524-529 - Ali Mirzaeian, Houman Homayoun, Avesta Sasan:
NESTA: Hamming Weight Compression-Based Neural Proc. EngineAli Mirzaeian. 530-537 - Baogang Zhang
Representable Matrices: Enabling High Accuracy Analog Computation for Inference of DNNs using Memristors. 538-543 - Zhanwei Zhong, Tung-Che Liang
Reliability-Oriented IEEE Std. 1687 Network Design and Block-Aware High-Level Synthesis for MEDA Biochips. 544-549 - Satoru Maruyama, Debraj Kundu, Shigeru Yamashita, Sudip Roy:
Optimization of Fluid Loading on Programmable Microfluidic Devices for Bio-protocol Execution. 550-555 - Ying Li, Jinyu Zhan, Wei Jiang, Junting Wu, Jianping Zhu:
An FPGA based Network Interface Card with Query Filter for Storage Nodes of Big Data Systems. 556-561 - Mengyuan Li, Xunzhao Yin, Xiaobo Sharon Hu
Nonvolatile and Energy-Efficient FeFET-Based Multiplier for Energy-Harvesting Devices. 562-567 - Patrick Sittel, John Wickerson, Martin Kumm, Peter Zipf
Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design. 568-573 - Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang:
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. 574-580 - Abdelrahman Hosny, Soheil Hashemi, Mohamed Shalan, Sherief Reda:
DRiLLS: Deep Reinforcement Learning for Logic Synthesis. 581-586 - Jeongwoo Heo, Taewhan Kim:
Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization. 587-592 - Hassaan Saadat, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
WEID: Worst-case Error Improvement in Approximate Dividers. 593-598 - Yi Guo, Heming Sun, Shinji Kimura:
Small-Area and Low-Power FPGA-Based Multipliers using Approximate Elementary Modules. 599-604 - Zahra Ebrahimi
LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy. 605-610 - He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu:
Scaled Population Arithmetic for Efficient Stochastic Computing. 611-616 - Masanori Hashimoto
Soft Error and Its Countermeasures in Terrestrial Environment. 617-622 - Grace Li Zhang
Timing Resilience for Efficient and Secure Circuits. 623-628 - Jürgen Teich, Behnaz Pourmohseni
Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems. 629-636 - Hussam Amrouch
NCFET to Rescue Technology Scaling: Opportunities and Challenges. 637-644 - Linghao Song
Parallelism in Deep Learning Accelerators. 645-650 - Christian Hakert
Software-Based Memory Analysis Environments for In-Memory Wear-Leveling. 651-658 - Shu Tanaka, Yoshiki Matsuda, Nozomu Togawa
Theory of Ising Machines and a Common Software Platform for Ising Machines. 659-666 - Satoshi Matsubara, Motomu Takatsu, Toshiyuki Miyazawa, Takayuki Shibasaki, Yasuhiro Watanabe, Kazuya Takemoto, Hirotaka Tamura:
Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its Applications. 667-672 - Chihiro Yoshimura, Masato Hayashi, Takashi Takemoto, Masanao Yamaoka:
CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem. 673-678
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