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ASAP 2006: Steamboat Springs, Colorado, USA
- 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA. IEEE Computer Society 2006, ISBN 0-7695-2682-9
Introduction
- Message from the Conference Chairs.
- Program Committee.
- External Referees.
Session 1: Configurable Computing Machines (Invited)
- Carl Ebeling:
Configurable Computing Platforms - Promises, Promises. 3-4 - Brent E. Nelson:
The Mythical CCM: In Search of Usable (and Resuable) FPGA-Based General Computing Machines. 5-14
Session 2: Processing, Storage and Network On-Chip
- Bo-Cheng Charles Lai, Patrick Schaumont
, Wei Qin, Ingrid Verbauwhede
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip. 15-18 - Júlio C. B. de Mattos, Stephan Wong, Luigi Carro
The Molen FemtoJava Engine. 19-22 - Antoine Scherrer, Antoine Fraboulet, Tanguy Risset:
A Generic Multi-Phase On-Chip Traffic Generation Environment. 23-27 - Sebastian Siegel, Renate Merker:
Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy. 28-32 - Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi:
NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm. 33-38
Session 3: Configurable Processors and Tools (Invited)
- Grant Martin:
Recent Developments in Configurable and Extensible Processors. 39-44 - Jeffrey M. Arnold:
Software Configurable Processors. 45-49 - Paul L. Master:
Reconfigurable Hardware and Software Architectural Constructs for the Enablement of Resilient Computing Systems. 50-55 - Drew Taussig, Andreas Hoffmann, Achim Nohl, Andrea Kroll:
Application Specific Processing: A Tools Approach. 56-64
Session 4: Parallel Connection Architectures
- Yedidya Hilewitz, Ruby B. Lee:
Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions. 65-72 - Aydin O. Balkan, Gang Qu, Uzi Vishkin:
A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing. 73-80 - Jun Tang, Tejas M. Bhatt, Vishwas Sundaramurthy:
Reconfigurable Shuffle Network Design in LDPC Decoders. 81-86 - Ricardo Santos, Rodolfo Azevedo
2D-VLIW: An Architecture Based on the Geometry of Computation. 87-94
Session 5: Parallel Processing and Arithmetic
- Chuan He, Guan Qin, Mi Lu, Wei Zhao
An Efficient Implementation of High-Accuracy Finite Difference Computing Engine on FPGAs. 95-98 - Lun Li, Alex Fit-Florea, Mitchell A. Thornton
Performance Evaluation of a Novel Direct Table Lookup Method and Architecture with Application to 16-bit Integer Functions. 99-104 - Tung N. Pham, Earl E. Swartzlander Jr.:
Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology. 105-108 - Aasavari Bhave, Eurípides Montagne, Edgar Granados:
Describing Quantum Circuits with Systolic Arrays. 109-113 - Elie H. Sarraf, Messaoud Ahmed Ouameur, Daniel Massicotte:
FPGA Implementation of Beamforming Receivers Based on MRC and NC-LMS for DS-CDMA System. 114-117 - Daesun Oh, Keshab K. Parhi
Low Complexity Design of High Speed Parallel Decision Feedback Equalizers. 118-124
Session 6: Arithmetic: Analysis and Implementation
- Thorsten von Sydow, Bernd Neumann, Holger Blume
Quantitative Analysis of Embedded FPGA-Architectures for Arithmetic. 125-131 - Sandeep B. Singh, Jayanta Biswas
A Cost Effective Pipelined Divider for Double Precision Floating Point Number. 132-137 - Ivan D. Castellanos, James E. Stine
A 64-bit Decimal Floating-Point Comparator. 138-144 - Francisco J. Jaime
Pipelined Range Reduction for Floating Point Numbers. 145-152
Session 7: 20th Anniversary Review-Array Processors (Invited)
- Earl E. Swartzlander Jr.:
Systolic FFT Processors: Past, Present and Future. 153-158 - John V. McCanny, Roger F. Woods
From Bit Level Systolic Arrays to HDTV Processor Chips. 159-162 - Richard Hughey, Andrea Di Blas:
The UCSC Kestrel Application-Unspecific Processor. 163-168 - Peter R. Cappello:
Multicore processors as Array Processors: Research Opportunities. 169-172
Session 8: Analysis and Optimizations
- Thomas B. Preußer, Rainer G. Spallek:
Analysis of a Fully-Scalable Digital Fractional Clock Divider. 173-177 - Mei Kang Qiu, Chun Xue
Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability. 178-181 - Woo Hyung Lee, Pinaki Mazumder:
Parallel Processing Based Power Reduction in a 256 State Viterbi Decoder. 182-185 - Ed F. Deprettere, Todor P. Stefanov
Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts. 186-190 - Philippe Clauss, Bénédicte Kenmei:
Polyhedral Modeling and Analysis of Memory Access Profiles. 191-198
Session 9: 20th Anniversary Review Optimizations and Applications (Invited)
- Graham A. Jullien:
Array Processing Using Alternate Arithmetic - A 20 Year Legacy. 199-204 - Florin Balasa, Per Gunnar Kjeldsberg, Martin Palkovic, Arnout Vandecappelle, Francky Catthoor:
Loop Transformation Methodologies for Array-Oriented Memory Management. 205-212 - Kung Yao, Flavio Lorenzelli:
An Overview of Systolic Array Concepts and Applications for Linear Algebra and Signal Processing. 213 - Daniel P. Lopresti:
Three Computationally Demanding Problems in Search of ASAP Solutions. 214-222
Session 10: Energy and Performance Optimizations
- Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil:
Parameterized Looped Schedules for Compact Representationof Execution Sequences. 223-230 - DaeGon Kim, Sanjay V. Rajopadhye:
An Improved Systolic Architecture for LU Decomposition. 231-238 - Shaoxiong Hua, Pushkin R. Pari, Gang Qu:
Dual-Processor Design of Energy Efficient Fault-Tolerant System. 239-244 - Giorgos Dimitrakopoulos
An Energy-Delay Efficient Subword Permutation Unit. 245-252
Session 11: Video, Coding and Cryptography
- Thomas Warsaw, Marcin Lukowiak:
Architecture design of an H.264/AVC decoder for real-time FPGA implementation. 253-256 - Antoni Portero
Dynamic Voltage Scaling for Power Efficient MPEG4-SP Implementation. 257-260 - Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Basten
Dynamic-SIMD for lens distortion compensation. 261-264 - Herwin Chan, Miguel Griot, Andres I. Vila Casado, Richard D. Wesel, Ingrid Verbauwhede
High Speed Channel Coding Architectures for the Uncoordinated OR Channel. 265-268 - Youtao Zhang, Jun Yang, Lan Gao:
Efficient Group KeyManagement with Tamper-resistant ISA Extensions. 269-274 - Guido Bertoni
Speeding Up AES By Extending a 32 bit Processor Instruction Set. 275-282
Session 12: Memory and Processor Synthesis
- Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Fabien Coelho:
Buffer and register allocation for memory space optimization. 283-290 - Pablo Ituero
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding. 291-296 - Feng Xian, Witawas Srisa-an, Hong Jiang:
Evaluating Hardware Support for Reference Counting Using Software Configurable Processors. 297-302 - Yiyu Tan, Chihang Yau, Anthony S. Fong:
Architectural Support on Object-Oriented Programming in a JAVA Processor. 303-310
Session 13: Matrix and Imaging Designs
- Humberto Calderon, Stamatis Vassiliadis:
Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit. 311-316 - Mythri Alle, Jayanta Biswas
High Performance VLSI Architecture Design for H.264 CAVLC Decoder. 317-322 - Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson:
An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets. 323-330 - Hritam Dutta, Frank Hannig
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. 331-340
Session 14: Cryptographic and Coding Applications
- Neil Smyth, Máire McLoone, John V. McCanny:
An Adaptable And Scalable Asymmetric Cryptographic Processor. 341-346 - Guerric Meurice de Dormale, Renaud Ambroise, David Bol, Jean-Jacques Quisquater, Jean-Didier Legat:
Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards. 347-353 - Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation. 354-359 - Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation. 360-367
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