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ANCS 2008: San Jose, California, USA
- Mark A. Franklin, Dhabaleswar K. Panda, Dimitrios Stiliadis:
Proceedings of the 2008 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2008, San Jose, California, USA, November 6-7, 2008. ACM 2008, ISBN 978-1-60558-346-4
Routing
- Jad Naous, David Erickson, G. Adam Covington, Guido Appenzeller, Nick McKeown:
Implementing an OpenFlow switch on the NetFPGA platform. 1-9 - Ben Wun, Patrick Crowley, Arun Raghunath:
Design of a scalable network programming framework. 10-18 - Charlie Wiseman, Jonathan S. Turner, Michela Becchi, Patrick Crowley, John D. DeHart, Mart Haitjema, Shakir James, Fred Kuhns, Jing Lu, Jyoti Parwatikar, Ritun Patney, Michael Wilson, Ken Wong, David Zar:
A remotely accessible network processor-based router for network experimentation. 20-29
Packet classification
- Yi-Hua E. Yang, Weirong Jiang
, Viktor K. Prasanna:
Compact architecture for high-throughput regular expression matching on FPGA. 30-39 - Yan Luo, Ke Xiang, Sanping Li:
Acceleration of decision tree searching for IP traffic classification. 40-49 - Michela Becchi, Patrick Crowley:
Efficient regular expression evaluation: theory to practice. 50-59
Multicore
- Danhua Guo, Guangdeng Liao, Laxmi N. Bhuyan, Bin Liu, Jianxun Jason Ding:
A scalable multithreaded L7-filter design for multi-core servers. 60-68 - Qiang Wu, Tilman Wolf
On runtime management in multi-core packet processing systems. 69-78 - Javier Verdú, Mario Nemirovsky, Mateo Valero
MultiLayer processing - an execution model for parallel stateful packet processing. 79-88
Measurements and switching
- Nan Hua, Bill Lin, Jun (Jim) Xu, Haiquan (Chuck) Zhao:
BRICK: a novel exact active statistics counter architecture. 89-98 - Paul Congdon, Matthew K. Farrens, Prasant Mohapatra:
Packet prediction for speculative cut-through switching. 99-108 - Faisal Khan, Lihua Yuan, Chen-Nee Chuah
A programmable architecture for scalable and real-time network traffic measurements. 109-118
Posters
- Qinghua Ye, Mike H. MacGregor:
Adaptive scheduling to maximize NIC throughput in a COTS router. 119-120 - Krishnendu Roy, Ramachandran Vaidyanathan, Jerry L. Trahan
Input-queued switches with logarithmic delay: necessary conditions and a reconfigurable scheduling algorithm. 121-122 - David Bermingham, Liu Zhen, Xiaojun Wang
SimNP: a flexible platform for the simulation of a network processing system. 123-124 - Yaxuan Qi, Zongwei Zhou, Baohua Yang, Fei He, Yibo Xue, Jun Li:
Towards effective network algorithms on multi-core network processors. 125-126 - Neda Beheshti, Yashar Ganjali, Monia Ghobadi, Nick McKeown, Jad Naous, Geoff Salmon:
Performing time-sensitive network experiments. 127-128 - Tilman Wolf
Data path credentials for high-performance capabilities-based networks. 129-130
Hardware implementations
- Alan Kennedy, Xiaojun Wang
Low power architecture for high speed packet classification. 131-140 - Hao Yu, Hubertus Franke, Giora Biran, Amit Golander, Terry Nelms, Brian M. Bass:
Stateful hardware decompression in networking environment. 141-150
I/O and custom networks
- Yunyue Lin, Qishi Wu:
On design of bandwidth scheduling algorithms for multiple data transfers in dedicated networks. 151-160 - Guangdeng Liao, Danhua Guo, Laxmi N. Bhuyan, Steve R. King:
Software techniques to improve virtualized I/O performance on multi-core systems. 161-170 - Florian Auernhammer, Patricia Sagmeister:
Design optimization of a highly parallel InfiniBand host channel adapter. 171-180
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