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Authors: Yang, Hongbo | Govindarajan, R. | Gao, Guang R. | Hu, Ziang

Article Type: Research Article

Abstract: Data cache in embedded systems plays the roles of both speeding up program execution and reducing power consumption. However, a hardware-only cache management scheme usually results in unsatisfactory cache utilization. In several new architectures, cache management details are accessible at instruction level, enabling the involvement of compiler for better cache performance. In particular, Intel XScale implemented the cache-locking mechanism, which enables the compiler to lock certain critical data in the cache and it is guaranteed that the locked data will not be evicted from the cache. In such an architecture, what-to-lock and when-to-lock are important issues to achieve good cache …performance. To this end, this paper gives a 0/1 knapsack problem formulation, which can be efficiently solved using a dynamic programming algorithm. We implemented this formulation in the MIPSpro compiler and our approach reduces both execution time and power consumption. The measured power and performance on an Xscale processor show that our method can achieve improved execution time than data prefetching at similar or reduced power consumption. Show more

Keywords: Compiler optimization, cache management, knapsack problem, Intel XScale, low power

Citation: Journal of Embedded Computing, vol. 1, no. 4, pp. 487-499, 2005