CERN Accelerating science

ATLAS Slides
Report number	ATL-DAQ-SLIDE-2024-523
Title	The Hardware implementation and Testing of the Full-function Global Common Module prototype for ATLAS Phase-II upgrade
Author(s)	Tang, Shaochun (Brookhaven National Laboratory (US)) ; Begel, Michael (Brookhaven National Laboratory (US)) ; Chatzianastasiou, George (Brookhaven National Laboratory (US)) ; Chen, Hucheng (Brookhaven National Laboratory (US)) ; Liu, Tiankuan (Brookhaven National Laboratory (US)) ; Qian, Weiming (Science and Technology Facilities Council STFC (GB)) ; Sankey, David (Science and Technology Facilities Council STFC (GB)) ; Silva Oliveira, Marcos Vinicius (Brookhaven National Laboratory (US)) ; Xu, Hao (Brookhaven National Laboratory (US))
Corporate author(s)	The ATLAS collaboration
Collaboration	ATLAS Collaboration
Submitted by	shaochun.tang@cern.ch on 04 Nov 2024
Subject category	Particle Physics - Experiment
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Abstract	The High Luminosity Large Hadron Collider (HL-LHC) is set to become operational in 2029, aiming to achieve instantaneous luminosities 5-7.5 times of the nominal value of the LHC. This poses significant challenges to the design of the Trigger and Data Acquisition systems. To address these challenges, a baseline architecture has been chosen for the ATLAS Phase-II upgrade, relying on a single-level hardware trigger known as the Level-0 Trigger. This trigger has a maximum rate of 1 MHz and a latency of 10 μs. The Global Trigger performs complex algorithms, akin to those currently used in Phase-I high-level trigger software (such as Topoclustering), on full-granularity calorimeter data. The Global Trigger is divided into three sublayers: the Multiplexer Processor (MUX) layer, the Global Event Processor (GEP) layer, and the Global to Central Trigger Processor interface (gCTPi). A full-function Global Common Module (GCM) hardware prototype has been designed to fulfill the requirements of all three sublayers of the Global Trigger, featuring different firmware loads. This GCM prototype, based on the ATCA form factor, incorporates two of the latest AMD (Xilinx) Versal Premium devices VP1802 and twenty Samtec 12-channel 25 Gb/s FireFly optical engines. These devices double the density of the Virtex UltraScale+ FPGA VU13P used in the previous design and include an integrated System-on-Chip (SoC) with a completely new architecture. The development of an ATCA blade with two large FPGAs and about 240 optical links running at 25 Gb/s is a very challenging task. The power integrity, signal integrity, and thermal simulations, hardware design considerations, functionalities, and performance test results of this GCM prototype will be presented.