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Author(s)
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Mazza, Giovanni (Turin U. ; INFN, Turin) ; Argirò, Stefano (Turin U. ; INFN, Turin) ; Borca, Cecilia (Turin U. ; INFN, Turin) ; Cometti, Simona (Turin U. ; INFN, Turin ; Polytech. Turin) ; Cossio, Fabio (Turin U. ; INFN, Turin) ; Dejardin, Marc (IRFU, Saclay) ; Dellacasa, Giulio (Turin U. ; INFN, Turin) ; Mignone, Marco (Turin U. ; INFN, Turin) ; Pastrone, Nadia (Turin U. ; INFN, Turin) ; Soldi, Dario (Turin U. ; INFN, Turin) ; Silvestrin, Luca (Padua U. ; INFN, Padua) ; Tedesco, Silvia (Turin U. ; INFN, Turin ; Polytech. Turin) ; Tessaro, Mario (INFN, Padua) ; Varela, Joao (LIP, Lisbon) ; Wheadon, Richard (Turin U. ; INFN, Turin) |
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Abstract
| The high-luminosity phase of operation of the CERN Large Hadron Collider (HL-LHC) will pose new challenges to the detectors and their readout electronics. In particular, the Compact Muon Solenoid (CMS) barrel electromagnetic calorimeter will require a full redesign of the electronic readout chain in order to cope with the increase in luminosity and trigger rate. In this framework, a new application-specific integrated circuit (ASIC) integrating A/D conversion, lossless data compression, and high-speed transmission has been developed and tested. The ASIC, named Lisboa-Torino Ecal Data Transmission Unit (LiTE-DTU), is designed in a commercial CMOS 65-nm process and embeds two 12-bit, 160-MS/s analog-to-digital converters (ADCs), a data selection and compression logic, and a 1.28-Gb/s output serial link. The high-speed 1.28-GHz clock is generated internally from the 160-MHz input by a clock multiplication phase-locked loop (PLL). The circuit has been designed implementing radiation-tolerant techniques in order to work in the harsh environment of the HL-LHC upgrade. The LiTE-DTU is currently in the preproduction phase. A sample of 600 chips has been tested and incorporated into front-end (FE) boards for systems performance testing. |