CERN Accelerating science

Published Articles
Title	The lpGBT PLL and CDR Architecture, Performance and SEE Robustness
Author(s)	Biereigel, Stefan (Brandenburg Tech. U. ; Leuven U. ; CERN) ; Kulis, Szymon (CERN) ; Francisco, Rui (CERN) ; Leitao, Pedro Vicente (CERN) ; Leroux, Paul (Leuven U.) ; Moreira, Paulo (CERN) ; Prinzie, Jeffrey (Leuven U.)
Publication	SISSA, 2020
Number of pages	5
In:	PoS TWEPP2019 (2020) 034
In:	TWEPP 2019 Topical Workshop on Electronics for Particle Physics, Santiago De Compostela, Spain, 2 - 6 Sep 2019, pp.034
DOI	10.22323/1.370.0034
Subject category	Detectors and Experimental Techniques
Abstract	We present the design, architecture and experimental results of the low jitter Clock and Data Recovery (CDR) and Phase Locked Loop (PLL) circuit in the Low-Power Gigabit Transceiver (lpGBT) ASIC. This circuit includes a low noise radiation-tolerant integrated LC-oscillator with a nominal frequency of 5.12 GHz to support a 10.24 Gbps uplink and a 2.56 Gbps downlink CDR. This CDR employs a novel loop architecture with a high-speed feed forward loop stabilization technique. A test circuit was fabricated in a 65 nm CMOS technology and has been tested experimentally for correct operation in the foreseen radiation environment.
Copyright/License	publication: © 2018-2024 The Authors (License: CC-BY-NC-ND-4.0)

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