| ATLAS Slides | |
| Report number | ATL-DAQ-SLIDE-2018-136 |
| Title | Design and testing of the high speed signal densely populated ATLAS calorimeter trigger board dedicate to jet identification |
| Author(s) |
Vieira De Souza, Julio (Institut fuer Physik, Universitaet Mainz) ; Bauss, Bruno (Institut fuer Physik, Universitaet Mainz) ; B\"uscher, Volker (Institut fuer Physik, Universitaet Mainz) ; Degele, Reinold (Institut fuer Physik, Universitaet Mainz) ; Herr, Holger (Institut fuer Physik, Universitaet Mainz) ; Rave, Stefan (Institut fuer Physik, Universitaet Mainz) ; Rocco, Elena (Institut fuer Physik, Universitaet Mainz) ; Schaefer, Uli (Johannes-Gutenberg-Universitaet Mainz (DE)) ; Tapprogge, Stefan (Institut fuer Physik, Universitaet Mainz) ; Weirich, Marcel (Institut fuer Physik, Universitaet Mainz) ; Borga, Andrea (FOM - Institute SAF Nikhef and University of Amsterdam/Nikhef) ; Kahra, Christian (Institut fuer Physik, Universitaet Mainz) |
| Corporate author(s) | The ATLAS collaboration |
| Submitted by | julio.souza@cern.ch on 26 Mar 2018 |
| Subject category | Particle Physics - Experiment |
| Accelerator/Facility, Experiment | CERN LHC ; ATLAS |
| Free keywords | Jet Feature Extractor ; jFEX ; L1Calo Phase-I ; High speed PCB |
| Abstract | The ATLAS experiment has planned a major upgrade in view of the enhanced luminosity of the beam delivered by the Large Hadron Collider (LHC) in 2021. As part of this, the trigger at Level-1 based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature Extractors (three in total), which each uses different physics objects for the trigger selection. The contribution focusses on the jet Feature EXtractor (jFEX) prototype. Up to a data volume of 2 TB/s has to be processed to provide jet identification (including large area jets) and measurements of global variables within few hundred nanoseconds latency budget. Such requirements translate into the use of large Field Programmable Gate Array (FPGA) with the largest number of Multi Gigabit Transceivers (MGTs) available on the market. The jFEX board prototype hosts four large FPGAs from the Xilinx Ultrascale family with 120 MGTs each, connected to 24 opto-electrical devices, resulting in a densely populated high speed signal board. MEGTRON6 was chosen as the material for the 24 layers jFEX board stackup because of its property of low transmission loss with high frequency signals (GHz range) and to further preserve the signal integrity special care has been put into the design accompanied by simulation to optimise the voltage drop and minimise the current density over the power planes. The jFEX prototype was delivered at the beginning of December and the preliminary results on the design validation and board characterisation will be reported. |
Rekord stworzony 2018-03-26, ostatnia modyfikacja 2018-03-28