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CERN Accelerating science

Published Articles
Title SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades
Author(s) Adolfsson, J (Lund U.) ; Pabon, A Ayala (Sao Paulo U.) ; Bregant, M (Sao Paulo U.) ; Britton, C (Oak Ridge) ; Brulin, G (Orsay, IPN) ; Carvalho, D (Sao Paulo U.) ; Chambert, V (Orsay, IPN) ; Chinellato, D (Campinas State U.) ; Espagnon, B (Orsay, IPN) ; Herrera, H D Hernandez (Sao Paulo U.) ; Ljubicic, T (Brookhaven) ; Mahmood, S M (Oslo U.) ; Mjörnmark, U (Lund U.) ; Moraes, D (Sao Paulo, Inst. Tech. Aeronautics) ; Munhoz, M G (Sao Paulo U.) ; Noël, G (Orsay, IPN) ; Oskarsson, A (Lund U.) ; Osterman, L (Lund U.) ; Pilyar, A (Dubna, JINR) ; Read, K (Oak Ridge) ; Ruette, A (Campinas State U.) ; Russo, P (Orsay, IPN) ; Sanches, B C S (Sao Paulo U.) ; Severo, L (Sao Paulo U.) ; Silvermyr, D (Lund U.) ; Suire, C (Orsay, IPN) ; Tambave, G J (Bergen U.) ; Tun-Lanoë, K M M (Orsay, IPN) ; Noije, W van (Sao Paulo U.) ; Velure, A (Bergen U.) ; Vereschagin, S (Dubna, JINR) ; Wanlin, E (Orsay, IPN) ; Weber, T O (Sao Paulo U., Guaratingueta) ; Zaporozhets, S (Dubna, JINR)
Publication 2017
Number of pages 3
In: JINST 12 (2017) C04008
In: Topical Workshop on Electronics for Particle Physics, Karlsruhe, Germany, 26 - 30 Sep 2016, pp.C04008
DOI 10.1088/1748-0221/12/04/C04008
Subject category Detectors and Experimental Techniques
Accelerator/Facility, Experiment CERN LHC ; ALICE
Abstract This paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply and provides 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel consists of a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC, a Digital Signal Processor provides digital filtering and compression capability. In the second prototype run both full chip and single test blocks were fabricated, allowing block characterization and full system behaviour studies. Experimental results are here presented showing agreement with requirements for both the blocks and the full chip.

Corresponding record in: Inspire


 Δημιουργία εγγραφής 2017-11-04, τελευταία τροποποίηση 2017-11-06