| ATLAS Slides | |
| Report number | ATL-DAQ-SLIDE-2016-374 |
| Title | FELIX - the new detector readout system for the ATLAS experiment |
| Author(s) |
Narevicius, Julia (Department of Particle Physics, The Weizmann Institute of Science) ; Anderson, John Thomas (Argonne National Laboratory) ; Borga, Andrea (FOM - Institute SAF Nikhef and University of Amsterdam/Nikhef) ; Boterenbrood, Hendrik (FOM - Institute SAF Nikhef and University of Amsterdam/Nikhef) ; Chen, Hucheng (Brookhaven National Laboratory (BNL)) ; Chen, Kai (Brookhaven National Laboratory (BNL)) ; Drake, Gary (Argonne National Laboratory) ; Donszelmann, Mark (Radboud University Nijmegen and NIKHEF) ; Francis, David (CERN) ; Gorini, Benedetto (CERN) ; Guest, Daniel (University of California, Irvine) ; Lanni, Francesco (Brookhaven National Laboratory (BNL)) ; Lehmann Miotto, Giovanna (CERN) ; Levinson, Lorne (Department of Particle Physics, The Weizmann Institute of Science) ; Roich, Alexander (Department of Particle Physics, The Weizmann Institute of Science) ; Schreuder, Frans Philip (FOM - Institute SAF Nikhef and University of Amsterdam/Nikhef) ; Schumacher, J\"orn (CERN) ; Vandelli, Wainer (CERN) ; Vermeulen, Jos (FOM - Institute SAF Nikhef and University of Amsterdam/Nikhef) ; Wu, Weihao (Brookhaven National Laboratory (BNL)) ; Zhang, Jinlong (Argonne National Laboratory) |
| Corporate author(s) | The ATLAS collaboration |
| Submitted to | 20th IEEE-NPSS Real Time Conference, Padua, Italy, 5 - 10 Jun 2016 |
| Submitted by | lorne.levinson@cern.ch on 05 Jul 2016 |
| Subject category | Particle Physics - Experiment |
| Accelerator/Facility, Experiment | CERN LHC ; ATLAS |
| Free keywords | DAQ GBT ROD ROS COTS PCIe FPGA E-link |
| Abstract | From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability. Different Front-end data types or different data sources can be routed to different network endpoints that handle that data type or source: e.g. event data, configuration, calibration, detector control, monitoring, etc. This reduces the diversity of custom hardware solutions in favour of software. Front-end connections can be either high bandwidth serial connections from FPGAs (e.g. 10 Gb/s) or those from the radiation tolerant CERN GBTx ASIC which aggregates many slower serial links onto one 5 Gb/s high speed link. Already in the Phase 1 Upgrade there will be about 2000 fiber connections. In addition to connections to a commodity network and Front-ends, FELIX receives Timing, Trigger and Control (TTC) information and distributes it with fixed latency to the GBTx connections. As part of the FELIX implementation, the firmware and Linux software for a high efficiency PCIe DMA engine has been developed. The system architecture of FELIX will be described; the results of the demonstrator program and the first prototype, along with future plans, will be presented. |
Registro creado el 2016-07-05, última modificación el 2016-12-20