Abstract: At present, the design of high-speed PCB is widely used in the fields of communication, computer, graphics and image processing. All high-tech value-added electronic product designs are pursuing low power consumption, low electromagnetic radiation, high reliability, miniaturization, and lightness. In order to achieve the above goals, via design is an important factor in high-speed PCB design. 1. General high-speed PCB material requirementsBefore understanding high-speed PCB design, you also need to understand other related knowledge, such as the selection of high-speed PCB materials. This is because the wrong selection of PCB materials will also have an adverse effect on the signal transmission performance of high-speed digital circuits.(1) Low loss, CAF resistance/heat resistance and mechanical toughness (viscosity) (good reliability) (2) Stable Dk/Df parameters (small coefficient of variation with frequency and environment) (3) Small tolerance of material thickness and glue content (good impedance control) (4) Low copper foil surface roughness (reduce loss) (5) Try to choose flat glass fiber cloth with small openings (reduce skew and loss) Next, we will give a more detailed explanation of the above 5 requirements for high-speed PCB materials. The integrity of high-speed signals is mainly related to impedance, transmission line loss and delay consistency. The signal integrity can be guaranteed if the appropriate waveform and eye diagram can be received at the receiving end. Therefore, the main parameter indicators for the selection of PCB materials for high-speed digital circuits are Dk, Df, loss, etc. Whether it is an analog circuit or a digital circuit, the dielectric constant Dk of the PCB material is an important parameter for material selection, because the Dk value is closely related to the actual circuit impedance value applied to the material. When the Dk value of the PCB material changes, whether it changes with frequency or temperature, the transmission line impedance of the circuit will change unexpectedly, which will have an adverse effect on the signal transmission performance of the high-speed digital circuit. If the Dk value of the PCB material presents different values for the harmonic components of different frequencies, the impedance will also have different resistance values at different frequencies. The unexpected changes in the Dk value and impedance will cause a certain degree of loss and frequency offset of the harmonic components, which will cause the analog harmonic components of the high-speed digital signal to be distorted, thereby reducing the integrity of the signal. Dispersion, which is closely related to the Dk value, is also a characteristic of the material. The smaller the Dk value changes with frequency, the smaller the dispersion, and the better it is for high-speed digital circuit applications. Various factors such as the polarization of the dielectric material, the loss of the material, and the surface roughness of the copper conductor in the high-frequency band will cause the dispersion of the circuit. Therefore, the Dk value of high-speed materials is required to be stable, and the smaller the fluctuation in its changes at different frequency bands and temperatures, the better. @Engineer, the selection of high-speed PCB materials needs to meet 5 major requirements, do you know?Transmission line loss usually includes three types: dielectric loss, conductor loss and radiation loss. Dielectric loss can also be called insulation layer loss. The insulation layer loss of PCB signals increases with the increase of frequency, especially with the frequency change of the high-order harmonic components of high-speed digital signals, which will produce serious amplitude attenuation, resulting in distortion of high-speed digital signals. Dielectric loss is proportional to the signal frequency, the square root of the dielectric constant Dk of the insulation layer, and the dielectric loss factor Df of the insulation layer. Conductor loss is related to the type of conductor (different types have different resistances), the physical size of the insulation layer and the conductor, and is proportional to the square root of the frequency; in PCB manufacturing, the main influence of using different substrates on conductor loss is caused by skin effect and surface roughness. When using different copper foils, the surface roughness of the signal line is different. Affected by the skin effect/depth, the length of the copper foil copper teeth will be directly related to the transmission quality of the high-speed signal. The shorter the copper tooth length, the better the high-speed signal transmission quality. Radiation loss is related to dielectric properties and is proportional to dielectric constant Dk, dielectric loss factor Df and the square root of frequency. Reminder: The better the material, the higher the cost. Engineers should strike a balance between design requirements, mass production and cost to achieve the best cost-effectiveness of the product.2. ViasVias are an important factor in multi-layer PCB design. A via is mainly composed of three parts: the hole; the pad area around the hole; and the POWER layer isolation area. The process of vias is to plate a layer of metal on the cylindrical surface of the via wall by chemical deposition to connect the copper foils that need to be connected in the middle layers, and the upper and lower surfaces of the vias are made into ordinary pad shapes, which can be directly connected to the upper and lower lines or not. Vias can serve as electrical connections, fixation or positioning devices. The schematic diagram of vias is shown in Figure 1. 3. ProcessingVia holes are generally divided into three categories: blind holes, buried holes and through holes. Blind holes refer to holes located on the top and bottom surfaces of printed circuit boards. They have a certain depth and are used to connect the surface circuits and the inner circuits below. The depth and diameter of the holes usually do not exceed a certain ratio. Buried holes refer to connecting holes located on the inner layer of printed circuit boards. They do not extend to the surface of the circuit board. Both blind holes and buried holes are located on the inner layer of the circuit board. They are completed by through-hole forming process before lamination. During the formation of through holes, several inner layers may be overlapped. Through holes, which pass through the entire circuit board, can be used to achieve internal interconnection or as mounting positioning holes for components. Since through holes are easier to implement in terms of process and have lower costs, they are generally used in printed circuit boards. The classification of vias is shown in Figure 2.4. Parasitic capacitance of viasThe vias themselves have parasitic capacitance to the ground. If the diameter of the isolation hole on the ground layer is D2, the diameter of the via pad is D1, the thickness of the PCB is T, and the dielectric constant of the board substrate is ε, then the parasitic capacitance of the vias is approximately:C =1.41εTD1/(D2-D1) The parasitic capacitance of the vias will have the main impact on the circuit by extending the rise time of the signal and reducing the speed of the circuit. The smaller the capacitance value, the smaller the impact. 5. Parasitic inductance of viasThe vias themselves have parasitic inductance. In the design of high-speed digital circuits, the harm caused by the parasitic inductance of the vias is often greater than the impact of the parasitic capacitance. The parasitic series inductance of the vias will weaken the role of the bypass capacitor and reduce the filtering effect of the entire power supply system. If L is the inductance of the via, h is the length of the via, and d is the diameter of the center drill hole, The parasitic inductance of the via is approximately: L=5.08h[ln(4h/d) 1] It can be seen from the formula that the diameter of the via has little effect on the inductance, while the length of the via has the greatest impact on the inductance. 6. Methods to reduce the adverse effects of the parasitic effects of vias in high-speed PCBs Usually in the process of high-speed PCB design, seemingly simple vias often bring great negative effects to the design of the circuit. So in order to reduce the adverse effects of the parasitic effects of vias, we can try to do the following in the design: (1) Regardless of the cost and signal quality, choose a reasonable size of the hole. For example, for the design of a 6-10 layer memory module PCB, it is better to choose a 10/20Mil (drilling/pad) via. For some small high-density circuit boards , you can also try to use an 8/18Mil via. Under current technical conditions, it is more difficult to use a smaller hole size. For vias of power or ground, you can consider using a larger size to reduce impedance. (2) From the above two equations, it can be concluded that using a thinner PCB board is beneficial to reducing the two parasitic parameters of vias. (3) The signal line has not changed on the PCB layer, that is, try not to use unnecessary vias. (4) The power and ground pins should be drilled nearby, and the leads between the vias and the pins should be as short as possible, because they will increase the inductance. At the same time, the power and ground leads should be as thick as possible to reduce impedance. (5) Place some ground vias near the vias of the signal layer change to provide the latest signal circuit. You can even place a large number of redundant ground vias on the PCB board. Of course, flexible design is also required. (6) The via model discussed above is the case where everyone has pads. Sometimes, we can reduce some keyboards or even cancel the layer. Especially when the via density is very high, it may cause a broken groove that cuts off the circuit in the copper layer.To solve this problem, in addition to moving the position of the via, you can also consider the through hole in the pad to reduce the size of the copper layer.7. Non-through-hole technologyNon-through-holes include blind holes and buried holes.In non-through-hole technology, the application of blind holes and buried holes can greatly reduce the size and quality of PCB, reduce the number of layers, improve electromagnetic compatibility, increase the characteristics of electronic products, reduce costs, and make the design work easier and faster. In traditional PCB design and processing, through holes will bring many problems. First, they occupy a large amount of effective space. Secondly, a large number of through holes in one place also cause huge obstacles to the inner layer routing of multi-layer PCBs. These through holes occupy the space required for routing. They densely pass through the surface of the power and ground layers, and also destroy the impedance characteristics of the power ground layer, making the power ground layer invalid. And the conventional mechanical drilling method will be 20 times the workload of non-through-hole technology.In PCB design, although the size of pads and vias has gradually decreased, if the thickness of the board layer does not decrease proportionally, the aspect ratio of the via will increase, and the increase in the aspect ratio of the via will reduce reliability. With the maturity of advanced laser drilling technology and plasma dry etching technology, it is possible to use small blind holes and small buried holes that are not through. If the diameter of these non-through holes is 0.3mm, the parasitic parameters brought are about 1/10 of the original conventional holes, which improves the reliability of the PCB. Due to the use of non-through hole technology, there will be very few large vias on the PCB, which can provide more space for routing. The remaining space can be used for large-area shielding to improve EMI/RFI performance. At the same time, more remaining space can also be used for partial shielding of devices and key network cables in the inner layer to give them the best electrical performance. The use of non-through holes can more conveniently fan out device pins, making it easy to route high-density pin devices (such as BGA packaged devices), shorten the connection length, and meet the timing requirements of high-speed circuits.8. Selection of vias in ordinary PCBs In ordinary PCB design, the parasitic capacitance and parasitic inductance of vias have little effect on PCB design. For 1-4 layer PCB design, it is generally better to use vias of 0.36mm/0.61mm/1.02mm (drilling/pad/POWER isolation area). Some signal lines with special requirements (such as power lines, ground lines, clock lines, etc.) can use vias of 0.41mm/0.81mm/1.32mm, and other sizes of vias can also be selected according to actual conditions. 9. Via design in high-speed PCBs Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to the design of circuits. In order to reduce the adverse effects of the parasitic effects of vias, the following can be done as much as possible in the design: (1) Choose a reasonable via size. For multi-layer PCB designs with normal density, it is better to use vias of 0.25mm/0.51mm/0.91mm (drilling/pad/POWER isolation area); for some high-density PCBs, 0.20mm/0.46mm/0.86mm vias can also be used, and non-through holes can also be tried; for vias of power or ground wires, larger sizes can be considered to reduce impedance; (2) The larger the POWER isolation area, the better. Considering the via density on the PCB, it is generally D1=D2 0.41; (3) The signal traces on the PCB should not change layers as much as possible, that is, minimize the number of vias; (4) Using a thinner PCB is conducive to reducing the two parasitic parameters of vias; (5) The pins of power and ground should be made into vias nearby, and the leads between the vias and the pins should be as short as possible, because they will increase the inductance. At the same time, the power and ground leads should be as thick as possible to reduce impedance;(6) Place some ground vias near the vias where the signal changes layers to provide a short-distance loop for the signal.Of course, specific problems need to be analyzed specifically during design. Considering both cost and signal quality, when designing high-speed PCBs, designers always hope that the vias are as small as possible, so that more wiring space can be left on the board. In addition, the smaller the via, the smaller its own parasitic capacitance is, and it is more suitable for high-speed circuits. In high-density PCB design, the use of non-through-holes and the reduction of via size also increase costs, and the size of vias cannot be reduced indefinitely. It is limited by the drilling and electroplating process technologies of PCB manufacturers, and should be given balanced consideration in the via design of high-speed PCBs.
Read More>>
