Search Results (42)

This article introduces an advanced theoretical approach, named the Trigonometric Kalman Filter (TKF), to enhance measurement accuracy for multi-head rotational encoders. Leveraging the processing capabilities of a Field-Programmable Gate Array (FPGA), the proposed TKF algorithm uses trigonometric functions and sophisticated signal fusion techniques to provide highly accurate real-time angle estimation with rapid response. The inclusion of the Coordinate Rotation Digital Computer (CORDIC) algorithm enables swift and efficient computation of trigonometric values, facilitating precise tracking of angular position and rotational speed. This approach represents a notable advancement in control systems, where high accuracy and minimal latency are essential for optimal performance. The paper addresses key challenges in angle measurement, particularly the signal fusion inaccuracies that often impede precision in high-demand applications. Implementing the TKF with an FPGA-based pure fixed-point method not only enhances computational efficiency but also significantly reduces latency when compared to conventional software-based solutions. This FPGA-based implementation is particularly advantageous in real-time applications where processing speed and accuracy are critical, and it demonstrates the effective integration of hardware acceleration in improving measurement fidelity. To validate the effectiveness of this approach, the TKF was rigorously tested on a precision drive control system, configured for a direct PMSM drive in an astronomical telescope mount equipped with a standard $0.5$m telescope frequently used by astronomers. This real-world application highlights the TKF’s ability to meet the stringent positioning and measurement accuracy requirements characteristic of astronomical observation, a field where minute angular adjustments are critical. The FPGA-based design enables high-frequency updates, essential for managing the minor, precise adjustments required for telescope control. The study includes a comprehensive computational analysis and experimental testing on an Altera Stratix FPGA board, presenting a detailed comparison of the TKF’s performance with other known methods, including fusion techniques such as differential methods, $\alpha$–$\beta$ filters, and related Kalman filtering applied to one sensors. The study demonstrates that the four-head fusion configuration of the TKF outperforms traditional methods in terms of measurement accuracy and responsiveness. Full article

This paper presents a novel recursive trigonometry (RT) technique for direct digital frequency synthesizer (DDFS) implementations. Traditional DDFS systems on field programmable gate arrays (FPGAs) either require a substantial amount of read-only memory (ROM) space to store reference values or depend on intricate angle rotation functions to approximate trigonometric values. The proposed RT technique offers a DDFS architecture without using the lookup table (LUT) method, and it can enhance signal accuracy and minimize power consumption. The effectiveness of the proposed RT technique has been implemented in a 13.5 kHz 16-bit DDFS with a minimum of 18.91 mW and was tested on a Lattice FPGA. The effectiveness of the proposed RT technology is assessed by using different FPGA platforms in terms of accuracy, hardware resource efficiency, and power consumption, especially in generating cosine waveforms. Full article

This paper presents a hardware-based audio encryption system using a 2D chaotic map and dynamic S-box design implemented on an Artix-7 FPGA platform. Three distinct chaotic maps—logistic–fraction (2D-LF), logistic–sine (2D-LS), and fraction–sine (2D-FS)—were investigated and implemented on an FPGA. The 2D-LF map was employed in the encryption system for its throughput and power efficiency performance. The proposed encryption system benefits from the randomness of chaotic sequences for block permutation and S-box substitution to enhance the diffusion and confusion properties of the encrypted speech signal. The system’s encryption strength is validated through performance evaluations, using the mean squared error (MSE), signal-to-noise ratio (SNR), correlation coefficients, and NIST randomness tests, which confirm the unpredictability of the encrypted speech signal. The hardware implementation results show a throughput of 2880 Mbps and power consumption of 0.13 W. Full article

The eigen-decomposition of a covariance matrix is a key step in the Direction of Arrival (DOA) estimation algorithms such as subspace classes. Eigen-decomposition using the parallel Jacobi algorithm implemented on FPGA offers excellent parallelism and real-time performance. Addressing the high complexity and resource consumption of the traditional parallel Jacobi algorithm implemented on FPGA, this study proposes an improved FPGA-based parallel Jacobi algorithm for eigen-decomposition. By analyzing the relationship between angle calculation and rotation during the Jacobi algorithm decomposition process, leveraging parallelism in the data processing, and based on the concepts of time-division multiplexing and parallel partition processing, this approach effectively reduces FPGA resource consumption. The improved parallel Jacobi algorithm is then applied to the classic DOA estimation algorithm, the MUSIC algorithm, and implemented on Xilinx’s Zynq FPGA. Experimental results demonstrate that this parallel approach can reduce resource consumption by approximately 75% compared to the traditional method but introduces little additional time consumption. The proposed method in this paper will solve the problem of great hardware consumption of eigen-decomposition based on FPGA in DOA applications. Full article

Electrocardiography (ECG) has emerged as a ubiquitous diagnostic tool for the identification and characterization of diverse cardiovascular pathologies. Wearable health monitoring devices, equipped with on-device biomedical artificial intelligence (AI) processors, have revolutionized the acquisition, analysis, and interpretation of ECG data. However, these systems necessitate AI processors that exhibit flexible configuration, facilitate portability, and demonstrate optimal performance in terms of power consumption and latency for the realization of various functionalities. To address these challenges, this study proposes an instruction-driven convolutional neural network (CNN) processor. This processor incorporates three key features: (1) An instruction-driven CNN processor to support versatile ECG-based application. (2) A Processing element (PE) array design that simultaneously considers parallelism and data reuse. (3) An activation unit based on the CORDIC algorithm, supporting both Tanh and Sigmoid computations. The design has been implemented using 110 nm CMOS process technology, occupying a die area of 1.35 mm² with 12.94 µW power consumption. It has been demonstrated with two typical ECG AI applications, including two-class (i.e., normal/abnormal) classification and five-class classification. The proposed 1-D CNN algorithm performs with a 97.95% accuracy for the two-class classification and 97.9% for the five-class classification, respectively. Full article

This paper presents a low-latency coordinate rotation digital computer (CORDIC) algorithm to accelerate the computation of arctangent functions, and it describes the corresponding iterative and pipelined architecture of this novel algorithm. As compared to the existing methods based on CORDIC, the proposed method can effectively reduce the number of iterations by dedicated pre-rotation and comparison processes. Moreover, the proposed CORDIC algorithm supports all vectors with arbitrary angles while maintaining convergence. By error analysis, the proposed algorithm can achieve the same accuracy as the conventional CORDIC algorithm during floating-point arctangent function computation and reduce the number of iterations by approximately 50%. This paper presents two new architectures—the iterative architecture, which can be more resource efficient, and the pipelined architecture, which can achieve a throughput rate of one datum per clock. Finally, the experimental comparison results indicate that the proposed method outperforms extant methods as it exhibits low latency, requires fewer resources to compute the arctangent function for floating-point inputs, and necessitates no digital signal processing (DSP) and memory for fixed-point inputs. Full article

Within the realm of digital signal processing and communication systems, FPGA-based CORDIC (Coordinate Rotation Digital Computer) processors play pivotal roles, applied in trigonometric calculations and vector operations. However, soft errors have become one of the major threats in high-reliability FPGA-based applications, potentially degrading performance and causing system failures. This paper proposes a fault classification and diagnosis method for FPGA-based CORDIC processors, leveraging Fast Fourier Transform (FFT) and Convolutional Neural Networks (CNNs). The approach involves constructing fault classification datasets, optimizing features extraction through FFT to shorten the time of diagnosis and improve the diagnostic accuracy, and employing CNNs for training and testing of faults diagnosis. Different CNN architectures are tested to explore and construct the optimal fault classifier. Experimental results encompassing simulation and implementation demonstrate the improved accuracy and efficiency in fault classification and diagnosis. The proposed method provides fault prediction with an accuracy of more than 98.6% and holds the potential to enhance the reliability and performance of FPGA-based CORDIC circuit systems, surpassing traditional fault diagnosis methods such as Sum of Square (SoS). Full article

With the rapid development of technologies like artificial intelligence, high-performance computing chips are playing an increasingly vital role. The inverse hyperbolic sine and inverse hyperbolic cosine functions are of utmost importance in fields such as image blur and robot joint control. Therefore, there is an urgent need for research into high-precision, high-performance hardware Intellectual Property (IP) for arcsinh and arccosh functions. To address this issue, this paper introduces a novel 128-bit low-latency floating-point hardware IP for arcsinh and arccosh functions, employing an enhanced Coordinate Rotation Digital Computer (CORDIC) algorithm, achieving a computation precision of 113 bits in just 32 computation cycles. This significantly enhances computational efficiency while reducing hardware implementation latency. The results indicate that, when compared to Python standard results, the calculated error of the proposed hardware IP does not exceed $8\times {10}^{-34}$. Furthermore, this paper synthesizes the completed IP using the TSMC 65 nm process, with a total IP area of 2.1056 mm${}^2$. Operating at a frequency of 300 MHz, its power is 22.4 mW. Finally, hardware implementation and resource analysis are conducted and compared on an Field Programmable Gate Array (FPGA). The results show that the improved algorithm trades a slight area increase for lower latency and higher accuracy. The designed hardware IP is expected to provide a more accurate and efficient computational tool for applications like image processing, thereby advancing technological development. Full article

The lock-in amplifier (LIA) is widely utilized to detect ultra-weak optical periodic signals based on the phase-sensitive and enhanced detecting theory. In this paper, we present an all-digital and universal embedded LIA platform that accurately and conveniently describes the spectrum generated by standard black bodies at various temperatures with different optical detectors. The proposed design significantly reduces the complexity and cost of traditional analog LIAs while maintaining accuracy. The LIA components are implemented using a single field programmable gate array (FPGA), offering flexibility to modify parameters for different situations. The normalized mean-square error (NMSE) of the captured spectra in the experiments is within 0.9% compared the theoretical values. Full article

To address the challenges of complex implementation structures and high hardware resource consumption in multiple-input multiple-output (MIMO) channel emulators, this paper proposes a hardware generation method for spatial–temporal correlated non-stationary channel fading. Firstly, a hardware generation architecture is developed for field-programmable gate array (FPGA) platforms, which can also reduce the complexity of the channel emulator. Secondly, an improved CORDIC method is introduced to reduce algorithm latency and hardware consumption while expanding the function convergence domain, with a relative error maintained at the level of 10-4. Furthermore, based on the idea of time-division multiplexing, an efficient hardware operation of a lower triangular matrix is adopted to minimize the consumption of hardware resources. Finally, the measured results demonstrate that the statistical characteristics of the channel fading generated by the proposed method are in good agreement with the theoretical ones, with an average error of less than 2%. Additionally, under identical simulation conditions, hardware resource consumption is reduced by 6.87%. These findings provide compelling evidence of the enhanced efficiency and accuracy in simulating MIMO channels achieved through the proposed method. Full article

With the continuous development of satellite payload and system-on-chip (SoC) technology, spaceborne real-time synthetic aperture radar (SAR) imaging systems play a crucial role in various defense and civilian domains, including Earth remote sensing, military reconnaissance, disaster mitigation, and resource exploration. However, designing high-performance and high-reliability SAR imaging systems that operate in harsh environmental conditions while adhering to strict size, weight, and power consumption constraints remains a significant challenge. In this paper, we introduce a spaceborne SAR imaging chip based on a SoC architecture with system fault-tolerant technology. The fault-tolerant SAR SoC architecture has a CPU, interface subsystem, memory subsystem, data transit subsystem, and data processing subsystem. The data processing subsystem, which includes fast Fourier transform (FFT) modules, coordinated rotation digital computer (CORDIC) modules (for phase factor calculation), and complex multiplication modules, is the most critical component and can achieve various modes of SAR imaging. Through analyzing the computational requirements of various modes of SAR, we found that FFT accounted for over 50% of the total computational workload in SAR imaging processing, while the CORDIC modules for phase factor generation accounted for around 30%. Therefore, ensuring the fault tolerance of these two modules is crucial. To address this issue, we propose a word-length optimization redundancy (WLOR) method to make the fixed-point pipelined FFT processors in FFT modules fault tolerant. Additionally, we propose a fault-tolerant pipeline CORDIC architecture utilizing error correction code (ECC) and sum of squares (SOS) check. For other parts of the SoC architecture, we propose a generic partial triple modular redundancy (TMR) hardening method based on the HITS algorithm to improve fault tolerance. Finally, we developed a fully automated FPGA-based fault injection platform to test the design’s effectiveness by injecting errors at arbitrary locations. The simulation results demonstrate that the proposed methods significantly improved the chip’s fault tolerance, making the SAR imaging chip safer and more reliable. We also implemented a prototype measurement system with a chip-included board and demonstrated the proposed design’s performance on the Chinese Gaofen-3 strip-map continuous imaging system. The chip requires 9.2 s, 50.6 s, and 7.4 s for a strip-map with 16,384 × 16,384 granularity, multi-channel strip-map with 65,536 × 8192 granularity, and multi-channel scan mode with 32,768 × 4096 granularity, respectively, and the system hardware consumes 6.9 W of power to process the SAR raw data. Full article

In the field of digital signal processing, such as in navigation and radar, a significant number of high-precision arctangent function calculations are required. Lookup tables, polynomial approximation, and single/double-precision floating-point Coordinate Rotation Digital Computer (CORDIC) algorithms are insufficient to meet the demands of practical applications, where both high precision and low latency are essential. In this paper, based on the concept of trading area for speed, a four-step parallel branch iteration CORDIC algorithm is proposed. Using this improved algorithm, a 128-bit quad-precision floating-point arctangent function is designed, and the hardware circuit implementation of the arctangent algorithm is realized. The results demonstrate that the improved algorithm can achieve 128-bit floating-point arctangent calculations in just 32 cycles, with a maximum error not exceeding $2\times {10}^{-34}$ rad. It possesses exceptionally high computational accuracy and efficiency. Furthermore, the hardware area of the arithmetic unit is approximately 0.6317 mm${}^2$, and the power consumption is about 40.6483 mW under the TSMC 65 nm process at a working frequency of 500 MHz. This design can be well suited for dedicated CORDIC processor chip applications. The research presented in this paper holds significant value for high-precision and rapid arctangent function calculations in radar, navigation, meteorology, and other fields. Full article

The radial artery reflects the largest amount of physiological and pathological information about the human body. However, ultrasound signal processing involves a large number of complex functions, and traditional digital signal processing can hardly meet the requirements of real-time processing of ultrasound data. The research aims to improve computational accuracy and reduce the hardware complexity of ultrasound signal processing systems. Firstly, this paper proposes to apply the coordinate rotation digital computer (CORDIC) algorithm to the whole radial artery ultrasound signal processing, combines the signal processing characteristics of each sub-module, and designs the dynamic filtering module based on the radix-4 CORDIC algorithm, the quadrature demodulation module based on the partitioned-hybrid CORDIC algorithm, and the dynamic range transformation module based on the improved scale-free CORDIC algorithm. A digital radial artery ultrasound imaging system was then built to verify the accuracy of the three sub-modules. The simulation results show that the use of the high-performance CORDIC algorithm can improve the accuracy of data processing. This provides a new idea for the real-time processing of ultrasound signals. Finally, radial artery ultrasound data were collected from 20 volunteers using different probe scanning modes at three reference positions. The vessel diameter measurements were averaged to verify the reliability of the CORDIC algorithm for radial artery ultrasound imaging, which has practical application value for computer-aided clinical diagnosis. Full article

This paper presents a new recursive trigonometric (RT) technique for Field-Programmable Gate Array (FPGA) design implementation. The traditional implementation of trigonometric functions on FPGAs requires a significant amount of data storage space to store numerous reference values in the lookup tables. Although the coordinate rotation digital computer (CORDIC) can reduce the required FPGA storage space, their implementation process can be very complex and time-consuming. The proposed RT technique aims to provide a new approach for generating trigonometric functions to improve communication accuracy and reduce response time in the FPGA. This new RT technique is based on the trigonometric transformation; the output is calculated directly from the input values, so its accuracy depends only on the accuracy of the inputs. The RT technique can prevent complex iterative calculations and reduce the computational errors caused by the scale factor K in the CORDIC. Its effectiveness in generating highly accurate cosine waveform is verified by simulation tests undertaken on an FPGA. Full article