Open AccessArticle

Application of Diverse Testing to Improve Integrated Circuit Test Yield and Quality

Chung-Huang Yeh

^1,*

Shou-Rong Chen

² and

Kan-Hsiang Liao

Intelligent Manufacturing Engineering, Minth University, Hsinchu 307, Taiwan

Department of Electrical Engineering, Chung-Hua University, Hsinchu 30012, Taiwan

Department of Accounting, Soochow University, Taipei 101, Taiwan

Author to whom correspondence should be addressed.

Eng 2024, 5(4), 3517-3539; https://doi.org/10.3390/eng5040183

Submission received: 30 October 2024 / Revised: 11 December 2024 / Accepted: 18 December 2024 / Published: 20 December 2024

(This article belongs to the Section Electrical and Electronic Engineering)

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Browse Figures

Figure 1
Errors in semiconductor manufacturing and testing processes. "> Figure 2
Distribution of chip delay times after wafer fabrication. "> Figure 3
Threshold test module. "> Figure 4
Impact of test guardband selection on test yield and test quality. "> Figure 5
Influence of test guardband on wafer yield and test quality during testing. "> Figure 6
Normal distribution of chip delay time after manufacturing and normal distribution of integrated circuit (IC) tester capability (OTA). "> Figure 7
Influence of automated test equipment (ATE) tester accuracy parameter (OTA) on test yield and quality. "> Figure 8
Test decision chart and decision-making methodology for diverse testing methods. "> Figure 9
Comparison of test results between the diverse test method (DTM) and traditional testing method (TTM). "> Figure 10
Improving test outcomes (300 ppm) with the diverse test method according to the IRDS 2023 table. "> Figure 11
Enhancement of the yield of high-quality product testing (10 ppm) through the diverse testing method. ">

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Abstract

This paper utilizes the digital integrated circuit testing model to compute the test yield curve of future wafers and explore the influence of test guardband (TGB) on quality and yield. With the passage of three years since the COVID-19 pandemic disrupted semiconductor production lines, the semiconductor manufacturing industry still faces chip shortages. Although initiatives such as the CHIPS and Science Act in the United States have helped stabilize chip supply chains, manufacturers still face inventory shortages and delayed deliveries. Moreover, the backwardness and inaccuracy of semiconductor test equipment have led to a decline in both test yield and wafer quality, resulting in reduced shipments. Therefore, to mitigate yield losses and enhance the test yield and shipment volume of semiconductor products, this paper proposes a diverse test method (DTM) to improve test outcomes through the alteration of the testing strategy and TGB adjustment. Furthermore, according to the wafer estimation table published in the IEEE International Roadmap for Devices and Systems (2023), the proposed DTM can effectively enhance the test yield of wafers and improve the testing capabilities of ATE testers (automatic test equipment). Consequently, suppliers can stabilize the chip supply chain and enhance their companies’ profits and reputation by improving chip test yield.

Keywords:

defect level; manufacturing yield; test yield; guardband test; threshold test; retest

1. Introduction

Transistors on integrated circuits (ICs) exponentially grow according to Moore’s law, with their number doubling every 18 to 24 months. When the number of transistors per unit area doubles, chip performance typically improves by 40% compared with the previous generation, which has resulted in fast and unpredictable development in the semiconductor industry [1,2,3,4]. As semiconductor manufacturing processes continue to advance rapidly, accurately forecasting future trends in IC product development is increasingly becoming challenging [5,6,7,8]. Consequently, this paper explores the interplay between semiconductor manufacturing capability parameters and testing capability parameters, leveraging statistical probability and the digital integrated circuit testing model (DITM) [9] to estimate IC manufacturing yield (Y_m) and testing yield (Y_t). Additionally, this paper employs an iterative calculation method (DITM) to precisely project future IC test yield curves, utilizing data from the IEEE International Equipment and Systems Roadmap (IRDS, 2023) [10].

As semiconductor test equipment (such as IC testers and ATE) capabilities fail to meet the yield and quality requirements of wafers, foundries (fabs) must seek more effective alternative testing methods to enhance testing quality and yield. To address the significant challenges posed by the low test quality and test yield of semiconductor wafers, various wafer-retesting schemes have been proposed across academia and industry. For instance, Kirmse et al. introduced a novel wafer probabilistic model [11] designed for the timely analysis of wafer operations and provided recommendations for wafer retesting. This approach promises quicker and more efficient detection of test errors. Jang, S.I. et al. [12] proposed an automated wafer-retesting system for enhancing test yields in wafer probing tests. They developed an artificial neural network model to differentiate between types of wafer failures and employed the error back-propagation algorithm for neural network training. This system has been implemented in mass production, resulting in an approximately 0.1% increase in total wafer yield and an approximately 80% reduction in total wafer test time. Furthermore, Jena, S.K. et al. [13] identified acceptable circuits (AcIC) through retesting, indirectly improving effective yield. The idea is to divide the testing process into two phases. In the first phase, this research paper follows the traditional testing process architecture and collects rejected circuits. In the second phase, all circuits that were rejected or not tested perfectly in the first phase undergo retesting using specific test patterns. Although this approach does not strictly adhere to the definition of AxIC, it can significantly improve yield. Additionally, Selg, H. et al. proposed [14] a mechanism that applies machine learning to effectively predict whether failed wafers should be retested. This method monitors wafers, providing data on initial and subsequent test runs. Experimental results using actual commercial product data validate the efficiency of the retest-success prediction method, leading to a significant optimization of manufacturing test time with a prediction accuracy of 78%. Building on the foundational concept of retesting [15], our research introduces the diverse testing method, which involves changing the testing process. In this method, we use iterative derivation calculations to estimate the test yield and quality of future wafers. Moreover, by leveraging the chip product forecast table released by the IEEE International Equipment and Systems Roadmap (IRDS, 2023), the proposed testing method can enhance the capabilities of semiconductor test equipment (ATE) and chip productivity. Furthermore, to meet consumers’ requirements for product quality, the proposed DTM can improve both test yield and quality, as well as facilitate the screening of high-quality, zero-defect products. To select high-quality chips, we modified the entire testing process and the testing specifications. One approach involves adjusting the test guard band (TGB) to minimize Type I (α) and Type II (β) errors, thereby extending the test time to identify reliable and marketable products. The proposed repeated testing method breaks the conventional theoretical concept of mutual exchange between yield and quality. Overall, the DTM mechanism can reduce the number of defective wafers and increase wafer shipments without reducing product yield. The proposed DTM method can be used to achieve the following improvements:

(1): Predict future wafer yield and quality;
(2): Strengthen the testing capabilities of the ATE;
(3): Reduce the occurrence of errors during the testing process and improve chip shipments and product quality; and
(4): Stabilize the chip supply chain.

2. Chip Manufacturing and IC Testing Errors

The purpose of semiconductor testing is to verify whether the chip logic function aligns with the test specification (TS). Defective chips undergo elimination during testing stages, while those passing the test proceed to customer shipment. Additionally, as depicted in Figure 1, the semiconductor fabrication plant (fab) produces a certain quantity (N) of IC wafers. Components meeting design specifications (DS) are termed good (G), while those failing to meet DS are labeled bad (B). The actual IC manufacturing yield Y_m is expressed as Y_m = G/N. Subsequently, the produced chips are sent to an IC testing facility for assessment.

However, issues such as the outdatedness or inaccuracy of the automated test equipment (ATE) or uncertainties within the testing process can arise. Consequently, wafers that pass the test (P, pass) may include defective wafers (B, bad), resulting in a Type II missing error (β). Similarly, wafers that fail (F, fail), as determined by the semiconductor test equipment (IC tester), may include good wafers (G, good), leading to a Type I killing error (α). Therefore, to enhance quality and meet customer demands, test engineers typically employ a TGB in IC testing. The TGB is defined as the difference between the TS and the DS, expressed as TGB = DS − TS [16,17].

2.1. IC Manufacturing Yield Calculation and Estimation

The semiconductor manufacturing process is intricate, involving thousands of steps. Alongside repeated exposure, development, ion implantation, etching, and other procedures, circuit diagrams of billions of transistors are manufactured in a small chip. Furthermore, as the semiconductor fab progresses through numerous process stations, the likelihood of defects increases. Complex interactions within the process and uncertainties in the program environment and procedures (such as errors in chemical concentrations or exposure during etching) may occur. Consequently, each chip produced by the fab may exhibit varying electrical characteristics. Therefore, this paper assumes that the chip’s delay time (a representation of its electrical parameters) follows a normal distribution (Figure 2), with an average value of μ_M and a standard deviation of σ_M.

Therefore, the electrical characteristics of the chip can be expressed as Chip(x) = N(x; μ_M, σ_M).

C h i p (x) = \frac{1}{σ_{M} \sqrt{2 π}} e^{\frac{- {(x - μ_{M})}^{2}}{2 {σ_{M}}^{2}}} d x,

(1)

The IC manufacturing yield (Y_m) is the probability of the area under the normal curve between the coordinates x = DS and x = −∞, i.e., P[−∞ < X < DS]. Y_m can be expressed as follows:

\begin{array}{l} I C M a n u f a c t u r i n g Y i e l d (Y_{m}) \\ = P [- \infty < X < D S] \\ = \int_{- \infty}^{D S} C h i p (x) d x \\ = \int_{- \infty}^{D S} (x; μ_{M}, σ_{M}) d x \\ = \int_{- \infty}^{D S} \frac{1}{σ_{M} \sqrt{2 π}} e^{\frac{- {(x - μ_{M})}^{2}}{2 {σ_{M}}^{2}}} d x \\ = \int_{- \infty}^{\frac{D S - μ_{M}}{σ_{M}}} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} d x \end{array}

(2)

With the continuous advancement of semiconductor process technology and the widespread adoption of artificial intelligence chips, the demand for advanced chips and technology has increased. In response to this increasing demand, this paper considers a scenario where a design house develops a high-end chip. Its chip DS is 1000 ps (1.0 GHz), and the characteristic electrical parameters of the device under test (DUT) can be expressed as N(x; μ_M = 800 ps, σ_M = 120 ps).

\begin{array}{l} I C M a n u f a c t u r i n g Y i e l d (Y_{m}) = P [- \infty < X < D S] \\ = \int_{- \infty}^{1000 ps} C h i p (x) d x \\ = \int_{- \infty}^{1000 ps} (x; 800 ps, 120 ps) d x \\ = \int_{- \infty}^{1000 ps} \frac{1}{120 ps \times \sqrt{2 π}} e^{\frac{- {(x - 800 p s)}^{2}}{2 \times ({120 p s)}^{2}}} d x \\ = \int_{- \infty}^{\frac{1000 p s - 800 p s}{120 p s}} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} d x = 95 %, \end{array}

As illustrated in Figure 2, the electrical time parameters (chip delay time) of the DUT are plotted on the x-axis, while the probability density of these electrical time parameters is depicted on the y-axis. The DUT clock rate is faster toward the left of the curve, while the DUT clock rate is slower toward the right. During the testing process, according to the chip’s DS parameters, the manufactured IC chips can be categorized as “good” or “bad” products. According to the aforementioned DUT characteristics and the derived Formula (1), the IC manufacturing yield can be obtained as Y_m = P[X < DS] = P [Good] = 95%. Here, P[−∞ < X < DS] indicates that the random parameter X lies within the probabilities of x = −∞ and x = DS.

2.2. Derivation and Estimation of IC Test Yield and Defect Levels

The wafer testing process is intricate and time-consuming, comprising (1) wafer testing, (2) packaging testing, and (3) characteristic analysis testing. These tests encompass parameter evaluations such as gate critical voltage, multi-domain critical voltage, bypass capacitance, metal field critical voltage, multi-layer resistance, metal multi-point contact resistance, diffusion layer resistance, contact resistance, and FET (field-effect transistor) parasitic leakage. To simplify the testing procedure, this paper employs chip delay time (threshold voltage) as a metric to assess the test yield and quality of the chip.

The primary aim of the testing is to verify whether the electrical characteristics of each die in the wafer align with the specifications stipulated by the design. A small red mark is added for identification if a product is deemed defective. Figure 3 shows the internal threshold test module of a general chip testing machine, which determines the quality of the chip by comparing signal speeds. The X parameter represents the chip delay time (DUT) within the circuit under test, and the ST (strobe) parameter denotes the signal time dispatched by the IC tester. The threshold voltage test sequence initially transmits the signal to the comparator of the chip IC tester (ATE). The ATE assesses the quality of the chip product according to the signal speed. If the test feedback signal is ST > X (X1 < X2), indicating that the ST time is later than the circuit under test, the DUT is classified as a good product (pass). Conversely, if the test feedback signal shows ST < X (X1 > X2), indicating that the ST time is earlier than the DUT, the DUT is classified as a problematic product (fail).

Before the chip exits the semiconductor fab or is dispatched for shipping, various functional tests are conducted on the DUT. These tests involve connecting specialized equipment (ATE) to the chip and delivering electrical signals to the chip. Moreover, the signal returned by the chip under test is captured to verify whether the chip aligns with the design requirements specified by the design house. Given the numerous uncertain factors inherent in the testing process, such as the IC tester (ATE) edge displacement, tester (ATE) inaccuracies, and engineer’s TGB settings, the testing capability of the semiconductor test equipment may not be a fixed value but rather a probability distribution. This paper assumes that the test capability of the IC tester follows a normal distribution, and its mean μ_T and standard deviation σ_T can be expressed as follows:

\begin{array}{l} I C T e s t e r (A T E, s e m i c o n d u c t o r t e s t e q u i p m e n t) \\ = \frac{1}{σ_{T} \sqrt{2 π}} e^{\frac{- {(y - μ_{T})}^{2}}{2 {σ_{T}}^{2}}} d y, \end{array}

(3)

The test yield is the ratio of the products that pass the test to all products, determined by the comparison of the IC tester comparator.

\begin{array}{l} If Y_{t} = P [pass] = P [X < ST], then \\ Y_{t} (%) (T T M) = I C T e s t Y i e l d \\ = \int_{- \infty}^{\infty} C h i p (x) \int_{x}^{\infty} T e s t e r (y) d y d x \\ = \int_{- \infty}^{\infty} \frac{1}{{\sqrt{2 π} σ}_{M}} e^{- \frac{1}{2} {(\frac{X - μ_{M}}{σ_{M}})}^{2}} \int_{x}^{\infty} \frac{1}{{\sqrt{2 π} σ}_{T}} e^{{- \frac{1}{2} (\frac{y - μ_{T}}{σ_{T}})}^{2}} d y d x \\ = \int_{- \infty}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} \int_{\frac{μ_{M} + σ_{M} x - μ_{T}}{σ_{T}}}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} y^{2}} d y d x, \end{array}

(4)

TTM refers to the traditional testing method, and the DUT undergoes testing only once during the test process.

2.3. Analysis for Defect-Level Estimation of IC

During the wafer manufacturing process, equipment abnormalities, errors in process steps, and incomplete execution of process steps can occur. Variations in process parameters and differences in semiconductor equipment environments contribute to the challenge of achieving 100% Y_m. For example, if a fab produces a batch of 1 million wafers, its Y_m might reach 90%. Without quality control from the test house, both good (90%) and defective products (10%) would be delivered to consumers. The 10% that are defective products (100,000 chips) not only damage the company’s reputation but also reduce its profits. In addition, wafer testing cannot be perfect, and testing errors exist in the IC tester (ATE) or in the testing process. Wafer testing without quality considerations is meaningless. Therefore, in addition to prioritizing test yield, addressing the test quality (Y_q) requirements of the wafer is crucial. Test errors originate from the inaccuracy of the IC tester (ATE), and the test operation procedures and engineers’ testing methods also directly influence the test results. Consequently, chips that cannot be sold (fail) include killing errors (α, Type I), which affects the product yield rate after testing. The sellable (pass) chips will contain missing errors (β, Type II), affecting the product quality after testing.

The quality of wafer products can generally be expressed by the defect level (DL), which represents the proportion of faulty wafers incorrectly included in the tested wafers, typically expressed in parts per million (ppm). The DL can be calculated using the following formula:

\begin{array}{l} D e f e c t L e v e l (p p m) = \frac{M i s s i n g E r r o r s (β, T y p e I I)}{T e s t q u a l i t y (Y_{q})} \\ = \frac{\int_{D S}^{\infty} \frac{1}{{\sqrt{2 π} σ}_{M}} e^{- \frac{1}{2} {(\frac{X - μ_{M}}{σ_{M}})}^{2}} \int_{x}^{\infty} \begin{matrix} \frac{1}{{\sqrt{2 π} σ}_{T}} e^{{- \frac{1}{2} (\frac{y - μ_{T}}{σ_{T}})}^{2}} dydx \end{matrix}}{\int_{- \infty}^{\infty} \frac{1}{{\sqrt{2 π} σ}_{M}} e^{- \frac{1}{2} {(\frac{X - μ_{M}}{σ_{M}})}^{2}} \int_{x}^{\infty} \begin{matrix} \frac{1}{{\sqrt{2 π} σ}_{T}} e^{{- \frac{1}{2} (\frac{y - μ_{T}}{σ_{T}})}^{2}} dydx \end{matrix}} \\ = \frac{\int_{\frac{D S - μ_{M}}{σ_{M}}}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} \int_{\frac{μ_{M} + σ_{M} x - μ_{T}}{σ_{T}}}^{\infty} \begin{matrix} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} y^{2}} dydx \end{matrix}}{\int_{- \infty}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} \int_{\frac{μ_{M} + σ_{M} x - μ_{T}}{σ_{T}}}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} y^{2}} d y d x}, \end{array}

(5)

where the level of missing errors is given by

\begin{array}{l} M i s s i n g E r r o r s P [B a d∣ P a s s] \\ = \int_{D S}^{\infty} C h i p (x) \int_{x}^{\infty} T e s t e r (y) d y d x \\ = \int_{D S}^{\infty} \frac{1}{{\sqrt{2 π} σ}_{M}} e^{- \frac{1}{2} {(\frac{X - μ_{M}}{σ_{M}})}^{2}} \int_{x}^{\infty} \frac{1}{{\sqrt{2 π} σ}_{T}} e^{{- \frac{1}{2} (\frac{y - μ_{T}}{σ_{T}})}^{2}} d y d x \\ = \int_{\frac{D S - μ_{M}}{σ_{M}}}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} \int_{\frac{μ_{M} + σ_{M} x - μ_{T}}{σ_{T}}}^{\infty} \begin{matrix} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} y^{2}} dydx, \end{matrix} \end{array}

(6)

The more a chip supplier invests in the testing phase, the greater the increase in testing time and manpower required. Additionally, higher test quality demands higher testing costs. Consequently, suppliers must strike a balance between quality and profitability to achieve profitable quality. For example, the quality of AMD-CPU notebook computers deemed acceptable by customers (measured by the DL, indicating the fraction of faulty chips among those that pass the test) typically falls within the range of 200 to 300 ppm (parts per million). However, aviation and automotive electronic products impose stricter reliability standards, with product quality requirements typically set at 10 ppm or less.

3. Impact of TGB on Test Results

Testing is a vital procedure in measuring chip quality; hence, test engineers must address the issue of TGB (Figure 4) during the testing process. TGB refers to the gap between the DS and the TS, defined as TGB = DS − TS. If the TGB shifts leftward, increasing the TGB will result in more killing errors but fewer missing errors. Consequently, as the TGB shifts leftward, test yield will decrease, while quality will improve. Conversely, if the TGB shifts rightward, reducing it, missing errors (β, Type II) will increase, and quality will decline, potentially leading to an increase in customer returns. Therefore, the test engineer’s decision regarding the TGB serves as a crucial determinant for gauging test yield and test quality. The test engineer’s handling of the TGB has a direct impact on the yield and quality of the product chip. Hence, during the testing process, besides considering the accuracy of the chip tester and the test outcomes, the guardband test must also be considered.

Consider a designed advanced CPU chip with DS = 1000 ps (1.0 GHz) and average value and standard deviation of the electrical characteristic parameters of the wafer defined as X ~ N (x; μ_M = 800 ps, σ_M = 120 ps). According to the earlier established Formula (1), the IC manufacturing yield of semiconductor wafers produced by the semiconductor fab can be calculated as Y_m = 95%. However, if the semiconductor IC company bypasses the testing process and delivers all the wafers to consumers, the DL will reach 50,000 ppm (1,000,000 × 5% = 50,000). This not only necessitates extensive recycling efforts for the company but also significantly tarnishes its reputation.

This experiment employs an IC tester with a characteristic parameter overall timing accuracy (OTA) = 120 ps (OTA = σ_T × 3 = 40 × 3 = 120 ps) to test the DUT, as depicted in Figure 5. Under a test quality (Y_q) of DL = 300 ppm and utilizing the TTM, the engineer configures the TS as μ_T = 921 ps (with TGB = DS − TS = 1000 − 921 = 79 ps), resulting in an obtained test yield of 83% (Y_t = P [Pass ] = P [X < ST] = 83%). Furthermore, this simulation increases the product quality threshold and sets the test quality (Y_q) to DL = 10 ppm (typical for biomedical electronics and avionics quality). Here, the engineer adjusts the TS to μ_T = 879 ps (increasing the TGB, TS = μ_T = 879 ps with TGB = DS − TS = 1000 − 879 = 121 ps), yielding a test yield of 79.7%. Analysis and comparison of the above results reveal that a greater distance between the TGBs leads to higher-quality chip products. Test engineers can increase the TGB to reduce the incidence of missing errors. While this may result in fewer wafer products passing the initial ATE test, it ensures the acquisition of high-quality wafer products.

\begin{array}{l} Case 1 : (T G B = D S - T S = 1000 - 921 = 79 p s) \\ Y_{t} (%) I C T e s t Y i e l d \\ = \int_{- \infty}^{\infty} C h i p (x) \int_{x}^{\infty} T e s t e r (y) d y d x \\ = \int_{- \infty}^{\infty} \frac{1}{\sqrt{2 π} \times 120 ps} e^{- \frac{1}{2} {(\frac{X - 800 p s}{120 p s})}^{2}} \int_{x}^{\infty} \frac{1}{\sqrt{2 π} \times 40 p s} e^{{- \frac{1}{2} (\frac{y - 921 p s}{40 p s})}^{2}} d y d x \\ = \int_{- \infty}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} \int_{\frac{800 p s + 120 p s \times x - 921 p s}{40 p s}}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} y^{2}} d y d x \\ = 83 % \end{array}

\begin{array}{l} D e f e c t L e v e l (p p m) \\ = \frac{\int_{1000 p s}^{\infty} \frac{1}{\sqrt{2 π} \times 120 p s} e^{- \frac{1}{2} {(\frac{X - 800 p s}{120 p s})}^{2}} \int_{x}^{\infty} \begin{matrix} \frac{1}{\sqrt{2 π} \times 40 p s} e^{{- \frac{1}{2} (\frac{y - 921 p s}{40 p s})}^{2}} dydx \end{matrix}}{\int_{- \infty}^{\infty} \frac{1}{\sqrt{2 π} \times 120 p s} e^{- \frac{1}{2} {(\frac{X - 800 p s}{120 p s})}^{2}} \int_{x}^{\infty} \begin{matrix} \frac{1}{\sqrt{2 π} \times 40 p s} e^{{- \frac{1}{2} (\frac{y - 921 p s}{40 p s})}^{2}} dydx \end{matrix}} \\ = \frac{\int_{\frac{1000 p s - 800 p s}{120 p s}}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} \int_{\frac{800 p s + 120 p s \times x - 921 p s}{40 p s}}^{\infty} \begin{matrix} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} y^{2}} dydx \end{matrix}}{\int_{- \infty}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} \int_{\frac{800 p s + 120 p s \times x - 921 p s}{40 p s}}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} y^{2}} d y d x} \\ = 300 ppm \end{array}

\begin{array}{l} Case 2 : (T G B = D S - T S = 1000 - 879 = 121 p s) \\ Y_{t} (%) I C T e s t Y i e l d \\ = \int_{- \infty}^{\infty} C h i p (x) \int_{x}^{\infty} T e s t e r (y) d y d x \\ = \int_{- \infty}^{\infty} \frac{1}{\sqrt{2 π} \times 120 ps} e^{- \frac{1}{2} {(\frac{X - 800 p s}{120 p s})}^{2}} \int_{x}^{\infty} \frac{1}{\sqrt{2 π} \times 40 p s} e^{{- \frac{1}{2} (\frac{y - 879 p s}{40 p s})}^{2}} d y d x \\ = \int_{- \infty}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} \int_{\frac{800 p s + 120 p s \times x - 879 p s}{40 p s}}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} y^{2}} d y d x \\ = 79.7 % \end{array}

\begin{array}{l} D e f e c t L e v e l (p p m) \\ = \frac{\int_{1000 p s}^{\infty} \frac{1}{\sqrt{2 π} \times 120 p s} e^{- \frac{1}{2} {(\frac{X - 800 p s}{120 p s})}^{2}} \int_{x}^{\infty} \begin{matrix} \frac{1}{\sqrt{2 π} \times 40 p s} e^{{- \frac{1}{2} (\frac{y - 879 p s}{40 p s})}^{2}} dydx \end{matrix}}{\int_{- \infty}^{\infty} \frac{1}{\sqrt{2 π} \times 120 p s} e^{- \frac{1}{2} {(\frac{X - 800 p s}{120 p s})}^{2}} \int_{x}^{\infty} \begin{matrix} \frac{1}{\sqrt{2 π} \times 40 p s} e^{{- \frac{1}{2} (\frac{y - 879 p s}{40 p s})}^{2}} dydx \end{matrix}} \\ = \frac{\int_{\frac{1000 p s - 800 p s}{120 p s}}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} \int_{\frac{800 p s + 120 p s \times x - 879 p s}{40 p s}}^{\infty} \begin{matrix} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} y^{2}} dydx \end{matrix}}{\int_{- \infty}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} \int_{\frac{800 p s + 120 p s \times x - 879 p s}{40 p s}}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} y^{2}} d y d x} \end{array}

From the above estimation results, employing stricter TSs will lead to a reduction in the test pass rate (increasing killing error (α, Type I)), but it will enhance test quality. Conversely, if the test engineer lowers the TGB, opting for looser TSs, the test pass rate will improve, but the test quality will decrease relatively (resulting in increased missing errors (β, Type II)). Consequently, under the same circuit characteristic parameters and IC tester (ATE) characteristic parameters, there exists a trade-off between test yield and test quality. However, achieving high yield and quality simultaneously through the TTM is not feasible.

Impact of IC Tester Accuracy (OTA) on Test Results

Over the past four decades, very-large-scale integration ultra-large IC chips have been integrating an increasing number of functions while reducing in size. However, as chip components shrink, product functionalities become increasingly complex. Consequently, while process variation accumulates, the permissible margin for errors within the process reduces (Figure 6). The rate of improvement in semiconductor manufacturing capacity is increasing by approximately 30% annually. However, the testing capabilities of semiconductor ATE are only growing at a rate of ~12% per year. If this trend persists, test quality will become progressively less reliable. Employing an ATE tester with poor accuracy [18,19,20] to test advanced ICs will result in deteriorating test yields over time, owing to the inaccuracies of the IC tester. Therefore, when predicting the test yield and test quality of wafers, test engineers should prioritize considerations such as the test capability of the IC tester and its accuracy (OTA) (including edge displacement of ATE).

According to the simulation data presented in Figure 7 and Table 1, different IC testers are utilized to test the wafer (DUT). When a low-precision ATE (OTA = σ_T × 3 = 100 × 3 = 300 ps) is employed alongside the TTM test method to test the component under test (TS = μ_T = 750 ps), a low yield test result of Y_t = 37.4% is obtained under the quality condition of 300 ppm (Y_q). Conversely, the use of a high-accuracy ATE (OTA = σ_T × 3 = 10 × 3 = 30 ps) with the TTM test method (TS = μ_T = 986 ps) to test the wafer (DUT) under the same quality conditions (300 ppm) (Y_q) yields high-yield test results (Y_t = 93.9%).

This improvement is attributed to the higher accuracy of the OTA IC tester (ATE), which effectively reduces testing errors such as killing errors and missing errors. However, ATE systems, designed to test various wafers, typically incur costs ranging from USD 1 million to USD 4 million. Additionally, the rental price of high-precision semiconductor IC testers (ATEs) is considerably high. Therefore, before embarking on test preparations, test engineers should not only consider the test yield and test quality of the chip products but also consider an IC tester that aligns with market costs based on customer quality requirements and market conditions.

4. Schedule of Diverse Testing

Over the past three decades, chip manufacturers have relied on rapid advancements in basic semiconductor technology to continuously enhance chip performance. However, once a chip product is developed, it must undergo reliable verification and testing before mass production. The emergence of artificial intelligence and the complexity of automotive electronics have resulted in a growing demand for chips. Wafer manufacturing in the nanometer era necessitates more advanced semiconductor manufacturing technology, yet the increasing complexity of these new technologies increases the costs of research, development, and manufacturing and intensifies the challenge of product verification. However, the persistent chip shortage issue since 2021 (due to COVID-19) has evolved into a structural problem that is challenging to resolve. Additionally, progress in IC testers has been slow, resulting in testing manufacturers being unable to utilize current IC testers (ATEs) and testing methods to distinguish the quality of products. To mitigate semiconductor yield losses and enhance the test yield and quality of semiconductor products, the semiconductor testing industry has proposed various wafer-retesting schemes. For instance, Greenberg, B.S. et al. developed a model [21] that computes the expected return of n retests. They estimated these probabilities according to retest results and considered the utilization of these estimates to design test plans. Additionally, Horng, S.C. et al. proposed a two-level approach grounded in ordinal optimization theory [22] to address the issue, aiming for reduced overkill and retesting within a reasonable computational timeframe. This approach has been applied to real semiconductor products to achieve optimal results and minimize excessive overkill while maintaining a tolerable retest rate. Furthermore, Cheng, K.C.C. et al. introduced a method [23] that analyzes the characteristics of test-induced defect patterns and outlines the features of machine learning algorithms capable of automatically detecting test-induced defects. This method enables the retesting of defective wafers caused by wafer testing to enhance yield. Multiple machine learning algorithms were employed to differentiate testing-induced defects from manufacturing-induced defects, with an average prediction accuracy exceeding 97%.

Moreover, to enhance the testing capabilities of the chip tester and improve chip quality, this paper introduces a DTM aimed at refining test outcomes. By adjusting the testing mechanism and appropriately shifting the TGB, coupled with iterative calculation methods to forecast future test yields, this paper devises a novel test process geared toward achieving high yield and quality results. This new approach involves retesting both the passed DUT components (P) and the failed DUT components (F), thereby reducing the likelihood of killing errors (α, Type I) and missing errors (β, Type II), through guardband testing and modifying the retest plan testing process. The proposed test plan is depicted in Figure 8, illustrating the initial test flow and the categorization of chips into pass (P, those that passed the initial test) and fail (F, those that failed the initial test).

\begin{array}{l} I Y_{t} = (D T M) I C T e s t Y i e l d (%) = P P + F P P + P F P \\ = \int_{- \infty}^{\infty} C h i p (x) \int_{x}^{\infty} T e s t e r (y, μ_{T 1}) d y \int_{x}^{\infty} T e s t e r (z, μ_{T 2}) d z d x \\ + \int_{- \infty}^{\infty} C h i p (x) \int_{- \infty}^{x} T e s t e r (y, μ_{T 1}) d y \int_{x}^{\infty} T e s t e r (z, μ_{T 2}) d z \int_{x}^{\infty} T e s t e r (w, μ_{T 3}) d w d x \\ + \int_{- \infty}^{\infty} C h i p (x) \int_{x}^{\infty} T e s t e r (y, μ_{T 1}) d y \int_{- \infty}^{x} T e s t e r (z, μ_{T 2}) d z \int_{x}^{\infty} T e s t e r (w, μ_{T 3}) d w d x \\ = \int_{- \infty}^{\infty} \frac{1}{σ_{M} \sqrt{2 π}} e^{\frac{- {(x - μ_{M})}^{2}}{2 {σ_{M}}^{2}}} \int_{x}^{\infty} \frac{1}{σ_{T} \sqrt{2 π}} e^{\frac{- {(y - μ_{T 1})}^{2}}{2 {σ_{T}}^{2}}} d y \int_{x}^{\infty} \frac{1}{σ_{T} \sqrt{2 π}} e^{\frac{- {(z - μ_{T 2})}^{2}}{2 {σ_{T}}^{2}}} d z d x \\ + \int_{- \infty}^{\infty} \frac{1}{σ_{M} \sqrt{2 π}} e^{\frac{- {(x - μ_{M})}^{2}}{2 {σ_{M}}^{2}}} \int_{- \infty}^{x} \frac{1}{σ_{T} \sqrt{2 π}} e^{\frac{- {(y - μ_{T 1})}^{2}}{2 {σ_{T}}^{2}}} d y \int_{x}^{\infty} \frac{1}{σ_{T} \sqrt{2 π}} e^{\frac{- {(z - μ_{T 2})}^{2}}{2 {σ_{T}}^{2}}} d z \int_{x}^{\infty} \frac{1}{σ_{T} \sqrt{2 π}} e^{\frac{- {(w - μ_{T 3})}^{2}}{2 {σ_{T}}^{2}}} d w d x \\ + \int_{- \infty}^{\infty} \frac{1}{σ_{M} \sqrt{2 π}} e^{\frac{- {(x - μ_{M})}^{2}}{2 {σ_{M}}^{2}}} \int_{x}^{\infty} \frac{1}{σ_{T} \sqrt{2 π}} e^{\frac{- {(y - μ_{T 1})}^{2}}{2 {σ_{T}}^{2}}} d y \int_{- \infty}^{x} \frac{1}{σ_{T} \sqrt{2 π}} e^{\frac{- {(z - μ_{T 2})}^{2}}{2 {σ_{T}}^{2}}} d z \int_{x}^{\infty} \frac{1}{σ_{T} \sqrt{2 π}} e^{\frac{- {(w - μ_{T 3})}^{2}}{2 {σ_{T}}^{2}}} d w d x \\ = \int_{- \infty}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} \int_{\frac{μ_{M} + {x σ}_{M} - μ_{T 1}}{σ_{T 1}}}^{\infty} \frac{1}{\sqrt{2 π}} e^{{- \frac{1}{2} (y)}^{2}} d y \int_{\frac{μ_{M} + {x σ}_{M} - μ_{T 2}}{σ_{T 2}}}^{\infty} \frac{1}{\sqrt{2 π}} e^{{- \frac{1}{2} (z)}^{2}} d z d x \\ + \int_{- \infty}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} \int_{- \infty}^{\frac{μ_{M} + {x σ}_{M} - μ_{T 1}}{σ_{T 1}}} \frac{1}{\sqrt{2 π}} e^{{- \frac{1}{2} (y)}^{2}} d y \int_{\frac{μ_{M} + {x σ}_{M} - μ_{T 2}}{σ_{T 2}}}^{\infty} \frac{1}{\sqrt{2 π}} e^{{- \frac{1}{2} (z)}^{2}} d z \int_{\frac{μ_{M} + {x σ}_{M} - μ_{T 3}}{σ_{T 3}}}^{\infty} \frac{1}{\sqrt{2 π}} e^{{- \frac{1}{2} (w)}^{2}} d w d x \\ + \int_{\infty}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} \int_{\frac{μ_{M} + {x σ}_{M} - μ_{T 1}}{σ_{T 1}}}^{\infty} \frac{1}{\sqrt{2 π}} e^{{- \frac{1}{2} (y)}^{2}} d y \int_{\infty}^{\frac{μ_{M} + {x σ}_{M} - μ_{T 2}}{σ_{T 2}}} \frac{1}{\sqrt{2 π}} e^{{- \frac{1}{2} (z)}^{2}} d z \int_{\frac{μ_{M} + {x σ}_{M} - μ_{T 3}}{σ_{T 3}}}^{\infty} \frac{1}{\sqrt{2 π}} e^{{- \frac{1}{2} (w)}^{2}} d w d x, \end{array}

(7)

\begin{array}{l} M i s s i n g E r r o r s = P [B a d∣ P a s s] \\ = \int_{D S}^{\infty} C h i p (x) \int_{x}^{\infty} T e s t e r (y, μ_{T 1}) d y \int_{x}^{\infty} T e s t e r (z, μ_{T 2}) d z d x \\ + \int_{D S}^{\infty} C h i p (x) \int_{- \infty}^{x} T e s t e r (y, μ_{T 1}) d y \int_{x}^{\infty} T e s t e r (z, μ_{T 2}) d z \int_{x}^{\infty} T e s t e r (w, μ_{T 3}) d w d x \\ + \int_{D S}^{\infty} C h i p (x) \int_{x}^{\infty} T e s t e r (y, μ_{T 1}) d y \int_{- \infty}^{x} T e s t e r (z, μ_{T 2}) d z \int_{x}^{\infty} T e s t e r (w, μ_{T 3}) d w d x \\ = \int_{D S}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} \int_{\frac{μ_{M} + {x σ}_{M} - μ_{T 1}}{σ_{T 1}}}^{\infty} \frac{1}{\sqrt{2 π}} e^{{- \frac{1}{2} (y)}^{2}} d y \int_{\frac{μ_{M} + {x σ}_{M} - μ_{T 2}}{σ_{T 2}}}^{\infty} \frac{1}{\sqrt{2 π}} e^{{- \frac{1}{2} (z)}^{2}} d z d x \\ + \int_{D S}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} \int_{- \infty}^{\frac{μ_{M} + {x σ}_{M} - μ_{T 1}}{σ_{T 1}}} \frac{1}{\sqrt{2 π}} e^{{- \frac{1}{2} (y)}^{2}} d y \int_{\frac{μ_{M} + {x σ}_{M} - μ_{T 2}}{σ_{T 2}}}^{\infty} \frac{1}{\sqrt{2 π}} e^{{- \frac{1}{2} (z)}^{2}} d z \int_{\frac{μ_{M} + {x σ}_{M} - μ_{T 3}}{σ_{T 2}}}^{\infty} \frac{1}{\sqrt{2 π}} e^{{- \frac{1}{2} (w)}^{2}} d w d x \\ + \int_{D S}^{\infty} \frac{1}{\sqrt{2 π}} e^{- \frac{1}{2} {(x)}^{2}} \int_{\frac{μ_{M} + {x σ}_{M} - μ_{T 1}}{σ_{T 1}}}^{\infty} \frac{1}{\sqrt{2 π}} e^{{- \frac{1}{2} (y)}^{2}} d y \int_{- \infty}^{\infty \frac{μ_{M} + {x σ}_{M} - μ_{T 2}}{σ_{T 2}}} \frac{1}{\sqrt{2 π}} e^{{- \frac{1}{2} (z)}^{2}} d z \int_{\frac{μ_{M} + {x σ}_{M} - μ_{T 3}}{σ_{T 2}}}^{\infty} \frac{1}{\sqrt{2 π}} e^{{- \frac{1}{2} (w)}^{2}} d w d x, \end{array}

(8)

Step 1. To ensure chip product quality, this simulation changed the testing process, retesting chips that passed the initial test (P). The aim of this retesting phase for previously passed chips (P) is to mitigate the missing error (β, Type II) in the product through TGB adjustment. Subsequently, wafers that successfully pass the second consecutive test are denoted as PP.

Step 2. However, chips (fail) that fail the initial test may include some portion of killing errors (α, Type I). To enhance test yield, this simulation retests wafers that failed the initial test (F). Following this step, the portion of the wafer that passes the test is referred to as FP.

Step 3. Afterward, this experiment observed that wafers PF, which pass the initial test but fail the second test, may also contain killing errors (α, Type I). Hence, this experiment retests the PF portion (after this step, the portion of the chip part that passes the test is referred to as PFP), employing the guardband’s adjustment mechanism to improve the test yield and product test quality.

The above method is termed “diverse testing method,” denoted as DTM.

4.1. Improving Test Results Through DTM

Figure 9 illustrates the results of an advanced chip in a CHIP circuit produced by a fab, where the DS of the component (DUT) is 1000 ps (1.0 GHz), and the electrical characteristics are N(x; μ_M = 800 ps, σ_M = 120 ps). According to the above conditions and electrical data, along with the iterative formula for estimation, a wafer Y_m of 95% is calculated. Subsequently, with the quality of wafer shipment set at 300 ppm, the IC tester ATE is employed to test the DUT through the TTM. The IC tester characteristic parameter OTA is set at 150 ps (OTA = σ_T × 3 = 50 × 3 = 150 ps), and the TS is defined as μ_T = 897 ps. Consequently, according to the above IC tester conditions, DUT characteristics, and data, Y_t is estimated as 77.2% (Figure 9 and Table 2).

To ensure compliance with the chip product quality standard (300 ppm), this simulation changes the testing mechanism and process, employing the DTM to assess the DUT. In this approach, various TSs (with μ_T = 936 ps) are applied for DUT evaluation. Considering the stipulated IC tester conditions (OTA = 150 ps) and DUT data, the test yield rate is determined as Y_t = 86.3%. Demonstrating adherence to the chip product quality standard (300 ppm), the utilization of the DTM leads to a 9.1% enhancement in Y_t (86.3% − 77.2% = 9.1%) compared with the TTM. This experiment implements the DTM, which involves extending the testing time and the testing process and incorporating DUT retesting. Retesting the DUT not only reduces the occurrence of killing errors but also enhances the performance of the IC tester by adjusting the TGB to increase the test yield. Consequently, under certain test quality conditions, DTM can effectively enhance Y_t. Moreover, given the slower pace of development of the IC tester (ATEs) compared with semiconductor manufacturing technology, multiple tests can also enhance the performance of IC testers (ATEs).

Subsequently, wafer shipment quality is enhanced to 10 ppm. The TS is set to μ_T = 840 ps, and the IC tester OTA remains at 150 ps, after which the TTM test method is employed to assess the DUT. According to previous estimations and calculations, Y_t is determined as 62.1%. Moreover, under the prerequisite of meeting wafer product quality standards (10 ppm), μ_T = 897 ps and tester OTA = 150 ps are employed with the DTM to test the DUT. The test yield rate is obtained as Y_t = 78.2%, marking a 16.1% increase compared with TTM methods (78.2% − 62.1% = 16.1%). The analysis underscores the significance of selecting an effective test process mechanism and appropriate TSs to mitigate the occurrence of accidental killing and misplacement errors. Hence, test engineers need to exercise caution when selecting the test method and determining the TGB size during the testing process to achieve optimal test results in terms of both yield and quality. Moreover, according to experimental findings, the adoption of the DTM and subsequent retesting of the DUT have proven beneficial. Particularly under stringent quality standards (10 ppm), DTM significantly enhances the testing yield and the performance of IC testers (ATE) for high-quality shipments. Overall, as chip quality requirements increase, DTM testing methods offer greater potential for yield rate enhancement.

4.2. Optimization of Iteration Numbers (Best Estimate of Y_t)

According to the ITRS 2015 [5], testing costs account for approximately 5% of the total production cost. For example, if the manufacturing cost of a wafer is USD 20, the testing cost would be USD 1. The international chip pricing strategy typically follows the 8:20 pricing model [24]; for example, if the chip cost is USD 8, the chip price would be USD 20. Assuming that Company “B” produces 10 million 1.0 GHz (1000 ps) wafers annually, with a unit price of USD 25 per wafer, the cost of each wafer is USD 10. The estimated cost of testing this batch of wafer products is approximately USD 5 million (10,000,000 × 10 × 5% = USD 5,000,000). By implementing a new testing method (DTM) that increases the test yield by 1% per test, Company “B” can sell an additional one hundred thousand chips annually (10,000,000 × 1% = 100,000), generating an additional profit of USD 2.5 million (10,000,000 × 25 × 1% = USD 2,500,000). If the test yield increases to 2% (10,000,000 × 25 × 2% = USD 5,000,000), the cost of product testing can be fully covered. However, if chips are retested excessively in pursuit of higher yields, the cost of testing may exceed the profit gained from the retesting process. This increases testing time and reduces company profitability. Therefore, test engineers must optimize the number of test iterations to balance costs and maximize the company’s profits effectively. Assume that Company “B” produces a batch of 10 million 1.0 GHz (1000 ps) wafers, each priced at USD 25, with circuit characteristic parameters modeled as X~N (x; μ_M = 800 ps, σ_M = 120 ps). According to the estimation equation provided, a manufacturing yield of 95% is achieved. If the wafers are tested using traditional methods (single test) with a tester selected at OTA = 150 ps and the DL set at 300 ppm, a test yield of 77.72% is obtained, as shown in Table 2. To meet the manufacturer’s requirements for high profits and yield, employing the DTM test method (Y_t = PP + PFP + FPP) achieves a test yield of 86.3%, representing an increase of 9.1% compared with the traditional method (86.3% − 77.72% = 9.1%). As a result, Company “B” can sell an additional 910,000 wafers annually (10,000,000 × 9.1% = 910,000), generating an extra annual revenue of USD 22.75 million (10,000,000 × 9.1%× 25 = USD 22.75 million). However, owing to extended lease times and the cost of repeated tests, the net additional revenue after deductions was USD 7.75 million (USD 22.75 million − USD 5 million − USD 5 million − USD 5 million =USD 7.75 million). To further improve yield, we apply an additional retest (one iteration, denoted as DTM₊₁) to the same batch of wafer products using a test specification of μ_T = 941 ps. This achieves a test yield of 87.1%, representing a 0.8% increase over DTM (87.1% − 86.3% = 0.8%). That is, each additional test iteration improves the yield by 0.8%. However, if the number of retests is increased by two iterations (denoted as DTM₊₂), further considerations is required. Using the test specification μ_T = 942 ps, the DTM₊₂ test yield is estimated to be 0.2% higher than the DTM₊₁ yield (87.3% − 87.1% = 0.2%).

From the above data analysis, the profit generated by additional DTM retests is insufficient to offset the cost of a single round of product testing unless the yield increases by at least 2%. That is, further increasing the number of DTM retests not only fails to enhance the company’s profitability but also leads reduces profits. Additionally, the experimental observations indicate that yield improvement is directly proportional to profit growth. However, under the same quality principles, as the number of repeated tests (iterations) increases, the rate of yield improvement gradually diminishes, with no significant large-scale gains. Therefore, when engineers plan the retesting process, they must carefully balance the time, labor, and material costs to maximize the company’s profits. Additionally, DTM results in a 9.1% increase in Yt compared with TTM (86.3% − 77.2% = 9.1%). Retesting the DUT not only reduces the likelihood of killing errors but also enhances the performance of the IC tester by adjusting the TGB, thereby improving the test yield under specific test quality conditions. According to the above results, DTM effectively enhances the testing machine capabilities and maximizes the economic benefits.

5. Estimating the Test Yield of IRDS (2023) Using DTM_S

Semiconductor IC testers (ATE) are characterized by inaccuracy and edge placement problems. During testing procedures, engineers’ decisions regarding the TGB directly influence the outcomes. Testing inaccuracies can lead to both killing errors and missing errors, thereby affecting test yield and quality and potentially harming a company’s profitability and reputation. Hence, this experiment adjusted the TGB and retested chips that initially failed the test (designated as “F”). This process effectively reduces the occurrence of killing errors (α, Type I). Similarly, the retesting of chips that initially passed the test (designated as “P”) significantly reduces missing errors (β, Type II). However, while retesting notably enhances test yield, it also indirectly increases test expenses. Therefore, to enhance test yield and corporate profits, weighing the associated costs is essential. Additionally, IC tester costs are contingent upon rental duration. The longer the IC tester is in use, the greater the cost for the company. However, considering that the test signal transmitted by the IC tester is exceedingly fast, the time lapse between a test and a retest may be less than a second. Thus, if the test process devised by the test engineer is accurate and efficient, and the test program is appropriately crafted, the time required for repeated testing can be minimized, rendering testing costs inconsequential.

The estimated data of chip products released by IRDS in 2023 are presented in Table 3. First, this paper focuses on the DUT manufactured in 2024, which encompasses product DSs ranging from 2.8 GHz (357 ps) to 3.4 GHz (294 ps). Consider the electrical characteristics of the DUT with a DS range of 2.8 GHz (357 ps), having an average μ_M of 216 ps and a standard deviation σ_M of 85 ps. Utilizing the previously derived Formula (1), a production yield of 95% OTA can be projected. Moreover, considering the parameter specifications of IC testers commonly utilized in the industry, this experiment employs a tester with OTA = 100 ps (OTA = σ_T × 3 = 100 ps) to assess the DUT. While maintaining the product quality DL at 300 ppm, the TS is configured to 289 ps. According to the iterative Formula (3), TTM yields a test yield of 78.8%. Furthermore, this experiment analyzes the electrical attributes of a DUT (2024) with a DS range of 3.4 GHz (294 ps), with a mean μ_M of 178 ps and a standard deviation σ_M of 70 ps. According to the previously derived Formula (1), configuring the TS to 223 ps can achieve a test yield of 72% through the TTM. Afterward, the future test yield and trend of wafer product development are estimated according to the 2023 IRDS data. The results (Figure 10 and Table 3) demonstrate the simulation outcomes and curve trends for the upcoming years. With the rapid advancement of advanced semiconductor processes contrasted with the sluggish development of IC testers, future IC test yields are expected to gradually decline over time.

To ensure the reliability of electronic products, it is necessary to eliminate all defective products from the total chip production and maintain rigorous quality control. However, maximizing the use of existing test equipment, which evolves slowly, to distinguish marketable products is an important issue. As shown in Figure 10, according to the forecast data table proposed by IRDS in 2023 and with a product quality DL of 300 ppm, a tester with OTA = 100 ps parameters is utilized. Two batches of wafers produced in 2026 are tested through the TTM, one with a clock frequency of 3.0 GHz (333 ps) and the other with 3.5 GHz (285 ps). Experimental findings reveal that owing to the limited capacity of the IC tester (ATE), the test yields using the TTM are Y_t = 77.3% (3.0 GHz) and Y_t = 71.1% (3.5 GHz). Furthermore, this experiment applies the DTM to examine the DUT. First, this experiment increases the TGB, trading off test yield for requisite quality. Concurrently, this experiment employs the DTM to test the DUT under identical quality conditions. Following DTM testing, this simulation observed an increase in test yield for wafers produced in 2026: Y_t = 86.4% (3.0 GHz) and Y_t = 83.3% (3.5 GHz). This represents a yield increase of approximately Y_t = 9.1% (3.0 GHz, 86.4% − 77.3% = 9.1%) and Y_t = 12.2% (3.5 GHz, 83.3% − 71.1% = 12.2%), respectively, compared with traditional testing. Moreover, under identical test conditions, DTM testing on wafers produced in 2034 (3.7 GHz) increases the test yield to Y_t = 82.4%. The experimental data demonstrate that under a test quality (Y_q) of DL = 300 ppm, DTM significantly enhances test yield, yielding an improvement of ~13.7% over traditional testing (82.4% − 68.7% = 13.7%).

Chips intended for automotive, aerospace, or medical electronics demand high reliability standards owing to safety imperatives. Consequently, the testing procedure entails greater time and expense. However, discerning high-quality products from the vast array of manufactured chips poses a significant challenge. This selection process not only tests the capabilities and expertise of test engineers but also presents a formidable challenge to the capabilities and methodologies of ATE testers. Consider a scenario in which a fab produces a batch of automotive chips, with a stringent quality requirement of 10 ppm. As depicted in Figure 11 and Table 3, the implementation of DTM can significantly enhance the test yield of wafers produced in 2034 (3.7 GHz) to 22.2% (70.2% (DTM) − 48% (TTM) = 22.2%). Overall, repetitive testing enhances chip product quality, test yield, and the performance of IC testers, leading to substantial improvements in test results. Incorporating additional testing steps and mechanisms reduces the number of defective chips and increases product output and enhances the overall profitability and reputation of the company. At this stage, this experiment only performed computer simulation estimation. From the analysis of the simulation results, this method has an excellent effect on improving the test yield and quality by saving manpower and reducing test costs. We believe that this set of theories and methods will be applied in the actual VLSI test environment shortly.

On the basis that the chip characteristics are normally distributed, this paper proposes an IC retesting solution to address the challenges associated with semi-conductor IC shipment and low yield. According to the above experiments, this paper’s proposed method (DTM) offers the following contributions:

(1): The method accurately estimates the test yield and test quality of future wafers through iterative derivation and calculation.
(2): DITM not only predicts and accurately depicts the test yield curve of future wafers but also enables tester manufacturers to enhance the testing capabilities and methods of ATE in advance according to the estimated data.
(3): The proposed method enhances the testing capabilities of the IC tester (ATE) and mitigates the occurrence of killing errors (α, Type I) and missing errors (β, Type II) in test chips.
(4): The proposed method challenges traditional theoretical concepts by simultaneously increasing output and quality, thereby increasing the company’s shipment volume and alleviating market chip shortages.
(5): The proposed method effectively improves the test yield, thereby significantly enhancing the yield of the tested products. This not only stabilizes the chip supply chain but also significantly enhances the company’s overall product profits and corporate reputation.
(6): The proposed DTM can achieve zero-defect and reliable products by moving the test guard band (TGB).

6. Conclusions

This paper employs the DITM for estimating test results in wafer testing. Through iterative derivation and calculation, the test yield and quality of the wafer are estimated. Additionally, this paper utilizes forecast data from the 2023 IRDS table to predict future trends in test yield. The DITM iterative calculation method not only forecasts the test yield curve of forthcoming wafers but also enables test houses to enhance and adjust tester functionalities and test methods according to the predicted curves. Despite the rapid progress in semiconductor manufacturing technology, the development of IC testers has progressed very slowly. Manufacturing technology and testing technology are evolving at different speeds, resulting in testing manufacturers being unable to effectively distinguish product quality using current IC testers (ATE) and testing methods. Hence, this paper introduces the DTM to enhance test outcomes. This method involves testing through various process mechanisms and dynamically adjusting the TGB.

A chip product estimation table was released through the IEEE International Roadmap for Devices and Systems (IRDS, 2023), DTM, and effective iterative calculations. Our research demonstrated that our proposed method could notably enhance the testing yield by over 20% compared with relatively outdated IC testers (ATEs). Furthermore, zero-defect high-quality products (zero-defect manufacturing, ZDM) are the ultimate goal pursued by the semiconductor industry. However, traditional chip testing must sacrifice the yield in exchange for a high yield. Considering aerospace and automotive electronics chips that require high reliability, the proposed DTM can extend the test time and change the test guard band (TGB). Retesting wafers that pass the test multiple times without sacrificing yield, the DTM reduces errors during the test process and adjusts the TGB to reduce the occurrence of killing and missing errors. Apart from enhancing the testing capabilities of the IC tester (ATE), through repeated testing, we searched for reliable products and obtained close to zero-defect products (10 ppm). Undoubtedly, DTM enhances the testing capabilities of IC testers and the quality of the tested products. Furthermore, considering the potential for future chip shortages and supply disruptions, DTM could help electronics manufacturers maintain increased productivity and stabilize the chip supply chain, resulting in a significant increase in company profit.

Author Contributions

Conceptualization, C.-H.Y.; Data curation, C.-H.Y.; Formal analysis, C.-H.Y.; Funding acquisition, C.-H.Y., S.-R.C. and K.-H.L.; Investigation, C.-H.Y.; Methodology, C.-H.Y.; Project administration, C.-H.Y., S.-R.C. and K.-H.L.; Resources, C.-H.Y.; Software, C.-H.Y.; Supervision, C.-H.Y., S.-R.C. and K.-H.L.; Validation, C.-H.Y.; Visualization, C.-H.Y., S.-R.C. and K.-H.L.; Writing—original draft, C.-H.Y.; Writing—review and editing, C.-H.Y., S.-R.C. and K.-H.L. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

All data are included within manuscript.

Acknowledgments

The authors would like to thank Jwu E. Chen for his invaluable contribution in both defining the model and implementing it mathematically. We would like to commemorate Chen’s contribution to academics with this article.

Conflicts of Interest

The authors declare no conflicts of interest.

Nomenclature

TGB	test guardband
DTM	diverse test method
Y_m	IC manufacturing yield (Y_m = G/N)
Y_t	IC testing yield
DITM	digital integrated circuit testing model
Y_q	test quality
DUT	the device under test
OTA	overall time accuracy of ATE
N	the semiconductor fabrication plant (fab) produces a certain quantity (N) of IC wafers
G	components meeting design specifications (DS)
B	failing to meet DS are labeled bad (B)
P	wafers that pass the test (P, pass)
F	wafers that fail (F, fail)
Type I (α)	errors killing error
Type II (β)	errors missing error
ATE	automatic test equipment
TS	test specification
DS	design specification
μ_M	the average value of the delay time chip of device under test (DUT)
σ_M	the standard deviation of the delay time dhip of device under test (DUT)
X1	The X parameter represents the chip delay time (DUT) within the circuit under test (X1)
ST	strobe parameter denotes the signal time dispatched by the IC tester (X2)
μ_T	the average value of the test capability of the IC tester
σ_T	the standard deviation of the test capability of the IC tester
TTM	the traditional testing method
DL	(defect level) indicating the fraction of faulty chips among those that pass the test
ppm	parts per million (ppm)
FET	field-effect transistor

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Figure 1. Errors in semiconductor manufacturing and testing processes.

Figure 2. Distribution of chip delay times after wafer fabrication.

Figure 3. Threshold test module.

Figure 4. Impact of test guardband selection on test yield and test quality.

Figure 5. Influence of test guardband on wafer yield and test quality during testing.

Figure 6. Normal distribution of chip delay time after manufacturing and normal distribution of integrated circuit (IC) tester capability (OTA).

Figure 7. Influence of automated test equipment (ATE) tester accuracy parameter (OTA) on test yield and quality.

Figure 8. Test decision chart and decision-making methodology for diverse testing methods.

Figure 9. Comparison of test results between the diverse test method (DTM) and traditional testing method (TTM).

Figure 10. Improving test outcomes (300 ppm) with the diverse test method according to the IRDS 2023 table.

Figure 11. Enhancement of the yield of high-quality product testing (10 ppm) through the diverse testing method.

Table 1. Comparison of yields and qualities obtained using different IC tester OTA (TTM).

σ_T (ps)	OTA = σ_T × 3	μ_T (ps)	Y_t (%)	Y_m (%)	DL (ppm)
10	30	986	93.9	95	300
20	60	966	91.4	95	300
30	90	944	87.8	95	300
40	120	921	83.0	95	300
50	150	896	77.0	95	300
60	180	870	70.0	95	300
70	210	843	62.2	95	300
80	240	814	53.9	95	300
90	270	783	45.5	95	300
100	300	750	37.4	95	300

Table 2. Estimated test results for different test methods.

DL		ppm	10	100	300
OTA = σ_T × 3 = 50 × 3		ps	150	150	150
$T T M$	Y_t	%	62.1	72	77.2
$T T M$	TS (μ_T)	ps	840	876	897
$D T M$	Y_t	%	78.2	83.6	86.3
$D T M$	TS (μ_T)	ps	897	922	936
Yield↑	Improve Y_t	%	16.1	11.6	9.1
OTA = σ_T × 3 = 40 × 3		ps	120	120	120
$T T M$	Y_t	%	72.6	79.7	83
$T T M$	TS (μ_T)	ps	876	905	921
$D T M$	Y_t	%	83.5	87.3	89
$D T M$	TS (μ_T)	ps	920	940	951
Yield↑	Improve Y_t	%	10.9	7.6	6
OTA = σ_T × 3 = 30 × 3		ps	90	90	90
$T T M$	Y_t	%	81.3	85.7	87.9
$T T M$	TS (μ_T)	ps	910	932	945
$D T M$	Y_t	%	87.7	90.2	91.4
$D T M$	TS (μ_T)	ps	941	957	966
Yield↑	Improve Y_t	%	6.4	4.5	3.5

Table 3. The future test yield and trend of wafer product development are estimated according to the 2023 IRDS data.

		Unit	2019	2022	2024	2026	2028	2030	2032	2034
Chip frequency		GHz	2.2–3.0	2.5–3.3	2.8–3.4	3.0–3.5	3.2–3.6	3.4–3.7	3.4–3.7	3.4–3.7
Device period		ps	454–333	400–303	357–294	333–285	313–278	294–270	294–270	294–270
μ_M		ps	274–201	242–183	216–178	201–172	189–168	177–163	177–163	177–163
σ_M		ps	108–79	95–72	85–70	79–68	75–66	70–64	70–64	70–64
OTA/3		ps	100	100	100	100	100	100	100	100
$T T M$	Y_t	%	84.8–77.3	82–73.6	78.8–72	77.3–71.1	74.5–70.1	72.8–68.7	72.8–68.7	72.8–68.7
$T T M$	TS (μ_T)	ps	390–265	334–233	289–223	265–214	243–207	224–198	224–198	224–198
	DL	ppm	300	300	300	300	300	300	300	300
$D T M$	Y_t	%	89.8–86.4	88.5–84.7	87–84	86.4–83.3	85–82.9	84.3–82.4	84.3–82.4	84.3–82.4
	TS (μ_T)	ps	414–291	359–260	315–251	291–241	270–234	251–226	251–226	251–226
	DL	ppm	300	300	300	300	300	300	300	300
Yield	Improve	%	5–9.1	6.5–11.1	8.2–12	9.1–12.2	10.5–12.8	11.5–13.7	11.5–13.7	11.5–13.7
$T T M$	Y_t	%	75.5–61.5	70.4–56	65–53.6	61.5–51.6	57.7–50	54.1–48	54.1–48	54.1–48
$T T M$	TS (μ_T)	ps	352–226	334–233	289–223	265–214	243–207	224–198	224–198	224–198
	DL	ppm	10	10	10	10	10	10	10	10
$D T M$	Y_t	%	84.9–77.9	82.2–74.6	79.7–73.4	77.9–72.6	75.5–71.7	73.9–70.2	73.9–70.2	73.9–70.2
	TS (μ_T)	ps	388–264	332–233	289–224	264–215	243–208	224–199	224–199	251–226
	DL	ppm	10	10	10	10	10	10	10	10
Yield	Improve	%	9.4–16.4	11.8–18.6	14.7–19.8	16.4–21	17.8–21,7	19.8–22.2	19.8–22.2	19.8–22.2

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Yeh, C.-H.; Chen, S.-R.; Liao, K.-H. Application of Diverse Testing to Improve Integrated Circuit Test Yield and Quality. Eng 2024, 5, 3517-3539. https://doi.org/10.3390/eng5040183

AMA Style

Yeh C-H, Chen S-R, Liao K-H. Application of Diverse Testing to Improve Integrated Circuit Test Yield and Quality. Eng. 2024; 5(4):3517-3539. https://doi.org/10.3390/eng5040183

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Yeh, Chung-Huang, Shou-Rong Chen, and Kan-Hsiang Liao. 2024. "Application of Diverse Testing to Improve Integrated Circuit Test Yield and Quality" Eng 5, no. 4: 3517-3539. https://doi.org/10.3390/eng5040183

APA Style

Yeh, C. -H., Chen, S. -R., & Liao, K. -H. (2024). Application of Diverse Testing to Improve Integrated Circuit Test Yield and Quality. Eng, 5(4), 3517-3539. https://doi.org/10.3390/eng5040183

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Application of Diverse Testing to Improve Integrated Circuit Test Yield and Quality

Abstract

1. Introduction

2. Chip Manufacturing and IC Testing Errors

2.1. IC Manufacturing Yield Calculation and Estimation

2.2. Derivation and Estimation of IC Test Yield and Defect Levels

2.3. Analysis for Defect-Level Estimation of IC

3. Impact of TGB on Test Results

Impact of IC Tester Accuracy (OTA) on Test Results

4. Schedule of Diverse Testing

4.1. Improving Test Results Through DTM

4.2. Optimization of Iteration Numbers (Best Estimate of Y_t)

5. Estimating the Test Yield of IRDS (2023) Using DTM_S

6. Conclusions

Author Contributions

Funding

Institutional Review Board Statement

Informed Consent Statement

Data Availability Statement

Acknowledgments

Conflicts of Interest

Nomenclature

References

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Article Menu

Application of Diverse Testing to Improve Integrated Circuit Test Yield and Quality

Abstract

1. Introduction

2. Chip Manufacturing and IC Testing Errors

2.1. IC Manufacturing Yield Calculation and Estimation

2.2. Derivation and Estimation of IC Test Yield and Defect Levels

2.3. Analysis for Defect-Level Estimation of IC

3. Impact of TGB on Test Results

Impact of IC Tester Accuracy (OTA) on Test Results

4. Schedule of Diverse Testing

4.1. Improving Test Results Through DTM

4.2. Optimization of Iteration Numbers (Best Estimate of Yt)

5. Estimating the Test Yield of IRDS (2023) Using DTMS

6. Conclusions

Author Contributions

Funding

Institutional Review Board Statement

Informed Consent Statement

Data Availability Statement

Acknowledgments

Conflicts of Interest

Nomenclature

References

Share and Cite

Article Metrics

Article Access Statistics

Further Information

Guidelines

MDPI Initiatives

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4.2. Optimization of Iteration Numbers (Best Estimate of Y_t)

5. Estimating the Test Yield of IRDS (2023) Using DTM_S