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Article

Novel Topology for Modified Boost Series and Parallel Switching Capacitor DC-DC Converter

by
Abdulaziz Alateeq
*,
Yasser Almalaq
and
Ayoob Alateeq
Department of Electrical Engineering, College of Engineering, University of Ha’il, Ha’il 2240, Saudi Arabia
*
Author to whom correspondence should be addressed.
Electronics 2024, 13(22), 4439; https://doi.org/10.3390/electronics13224439
Submission received: 5 October 2024 / Revised: 1 November 2024 / Accepted: 5 November 2024 / Published: 13 November 2024
(This article belongs to the Section Power Electronics)
Browse Figures
Figure 1
<p>Makowsli’s topology of boost converter during (<b>a</b>) phase 1, (<b>b</b>) phase 2.</p> "> Figure 2
<p>The novel topology of boost converter during (<b>a</b>) phase 1 and (<b>b</b>) phase 2.</p> "> Figure 3
<p>Switching capacitor converter with converter output impedance.</p> "> Figure 4
<p>Novel topology of boost DC-DC converter.</p> "> Figure 5
<p>Hand calculation and simulation for the novel topology using linear capacitors simulation and experimental results.</p> "> Figure 6
<p>Output voltage results for Makowski and the novel topologies at simulation.</p> "> Figure 7
<p>Output voltage results for Makowski and novel topologies at the lab.</p> "> Figure 8
<p>Hysteresis loop for ferroelectric capacitor.</p> "> Figure 9
<p>The novel topology of a boost converter with a nonlinear capacitor during (<b>a</b>) phase 1 and (<b>b</b>) phase 2.</p> "> Figure 10
<p>The novel topology of a boost converter with a nonlinear capacitor built in the lab.</p> "> Figure 11
<p>Simulation results for converter output voltage for Makowski’s topology, novel topology, and novel topology with nonlinear capacitors.</p> "> Figure 12
<p>Lab results for converter output voltage for Makowski’s topology, novel topology, and novel topology with nonlinear capacitors.</p> ">
Versions Notes

Abstract

:
Theoretical and experimental work for a novel topology of DC-DC boost switching capacitor converter is introduced in this paper. This new design is an adjustment for boost series and parallel topology developed by Makowski. Thus, a comparison between the two designs presented in this paper aims to highlight the improvement in the conversion rate of the boost converter’s output voltage while using the same number and size of capacitors. Converter analyses for both with and without load are presented. Also, a boost converter with a nonlinear ferroelectric capacitor is presented to further increase the boost converter conversion rate using advantages of the ferroelectric capacitors, such as their big dielectric constant and polarization reversal.

1. Introduction

DC to DC converters are very important applications in power electronics due to their integration with other scopes such as power systems, control systems, analog circuits, electronic circuits, etc. This paper presents a novel topology of a DC-DC boost converter that can be used for low-power applications such as IC circuits. DC-DC converters can be classified into two categories: isolated and non-isolated converters, which can also be divided into different types.
First, non-isolated converters, which can be divided into inductor-based, such as buck and boost converters, and capacitor-based, such as switching capacitor converters. Inductor-based converters, which can be applied for high-power applications, are not applicable to this work due to the existence of inductors, which present major drawbacks in integrating these converters directly on a chip because of the difficulty of integrating large-quality factor inductors in VLSI chip technology. In addition, electromagnetic interference is due to inductor emission and complications of installing inductors on IC circuits due to poor isolation from substrate and large resistance because of limitations on the thickness of metallization. For those reasons, a capacitor-based DC-DC converter is applied for this work. It was first introduced in 1974 as a charge pump converter to boost voltage in flash memory and EEPROM memory [1]. Nevertheless, because of the small sizes of capacitors that can be used in the CMOS, this type of converter is not able to supply enough power as a boost converter does. The first actual non-isolated DC-DC switching capacitor converters were introduced in 1990 by a group of researchers in Japan [2]. This new approach to DC-DC converters gave the opportunity to develop a converter that avoided issues associated with inductor-based converters and supplied enough power to the load.
The second type of DC-DC converters are isolated converters such as flyback, bush pulls, and full bridge converters. Ref. [3] presents an example of isolated DC-DC converters by combining two H-bridge converters. This type of converter converts DC signals to AC using switches that are controlled by PWM waveforms. Since this H-bridge converter supports a dual power flow, combining two of them will form an isolated DC-DC converter. However, due to the converter’s large size and difficulties of installing it in IC circuits, it is not applicable to this work.
After the emergence of the first non-isolated DC-DC switching capacitor converter, Makowski developed series and parallel boost converters, which have a conversion rate of K + 1, where K represents the number of used capacitors [4]. During the first phase, capacitors are connected in parallel with the voltage source, so they are fully charged with (Vin). During the second phase, those capacitors, which are charged with (Vin), and voltage source are connected in series to the summit capacitors’ initial voltages and connected them in parallel with the load as shown in Figure 1.
This paper presents a modified topology, as shown in Figure 2, for the boost series and parallel converter to increase its conversion rate by reconfiguring capacitor connections with the voltage source, as it will be explained in detail in the next section. Then, Seeman’s switching capacitor analysis approach [5] is utilized in this paper to analyze the output voltage of the converter in case of a load connected to the converter. In addition to the novel topology, ferroelectric capacitors are used to increase the conversion rate of boost converters [6] by using their special characteristics, which are the large constant of dielectric and reversal polarization of switching current.

2. The Boost Converter Design

The novel topology shown in Figure 2 has two types of capacitors. The first type is known as charge transfer capacitors, which transfer charges from source to load through the control of switches. The second type is a filter capacitor, which is connected in parallel with the load to smooth and filter output voltage [7,8,9,10,11,12,13]. In addition to that, this topology has 12 switches that control the connection of capacitors to form converter phase one and phase two topologies.
During the first phase, switches (SW1, SW2, SW3, SW4, SW7, SW11, and SW12) are ‘ON’ while others are ‘OFF’, to form the converter modified topology in Figure 2a. During this phase, charge transfer capacitors C 1 , C 2 , and C 3 are connected in parallel with the series combination of voltage source and C 4 , which is fully charged with (Vin) from phase two [14,15,16,17,18,19,20,21]. As a result of this connection, charge transfer capacitors of C 1 ,   C 2 , and C 3 are charged with the voltage source and initial voltage of C 4   V i n + V C 4 , unlike with Makowski’s topology in reference [4], where charge transfer capacitors of C 1 ,   C 2 ,   C 3 , and C 4 are charged with V i n only.
During the second phase, switches (SW5, SW6, SW8, SW9, and SW10) are ‘ON’ while others are ‘OFF’. The voltage source is connected in parallel with capacitor C 4   as in Figure 2b, so it can be recharged with V i n , which makes V C 4 = V i n in the case of no load. Other charge transfer capacitors C 1 , C 2 , and C 3 , which are charged during the first phase with a voltage of V i n + V C 4 , are connected in series to summit initial voltages across those capacitors and dump them to the load by parallel connection with filter capacitor C L .
In the case of no load where ( V C 4 = V i n ), the output voltage of the converter modified topology is expressed as follows:
V O = V C 1 + V C 2 + V C 3 = 3 ∗ (   2 V i n ) = 6   V i n
Moreover, the output voltage at Makowski’s topology in the case of no load is expressed as follows:
V O = K + 1 ∗ V i n = 4 + 1   ∗ V i n = 5   V i n
where K represents the capacitor number. By comparing output voltages between Equations (1) and (2), the novel topology of the DC-DC converter shows a better conversion rate than Makowski topology [4], if the number of capacitors used in this novel topology of the boost converter is four or more.
If the number of capacitors used in those topologies is three, the conversion rate between the two topologies is the same. From Equation (1):
V O = V C 2 + V C 3 = 4   V i n
From Equation (2):
V O = K + 1 ∗ V i n = 3 + 1 ∗ V i n = 4   V i n
In the case of two capacitors used in both topologies, Makowski’s topology shows a better conversion rate.
In the case of no load, the novel topology has an output voltage equal to 6   V i n . This ideal output voltage is divided between the series resistances of R L and R l o s s , which represent the converter losses that can be calculated using Seeman’s approach [5]. Moreover, the voltage across R L represents the converter’s actual output voltage, as shown in Figure 3.
The loss resistance R l o s s can be calculated using Seeman’s approach as follows:
R l o s s = ∑ a C i 2 f s w ∗ C i
where a C i is the charge multiplier = q i / q O (where q i is the input charge q O   is the output charge) and F s w is the switching frequency.
The charge multiplier for each capacitor has been calculated, which is equal to 1. Hence, R l o s s can be calculated as follows:
R L o s s = 1 F s w   1 C 2 + 1 C 3 + 1 C 4  
The actual converter output voltage is expressed as follows:
V O = 3 ∗ V i n + V C 1 ∗ R L R L + R l o s s
where 3 represents the number of capacitors, which are C 1 , C 2 , and C 3 as in Figure 4. Each one of these capacitors is charged with V i n + V C 4 during the first phase.
Data introduced in Figure 5 and Table 1 are comparisons between simulation and hand calculation results for the novel boost converter [22,23,24,25,26,27]. Those results show a decent correlation between them, which means that the analysis of the converter with Seeman’s approach is accurate and appropriately applied.

3. Simulation and Experimental Results

3.1. Converter Simulation Results

LTSPICE software (Version (x64): 24.0.9) has been used to run and simulate Makowski’s and the novel topologies of DC-DC boost converters. Switching between first and second topologies is executed via idea switches, which are accessible in the software [28,29,30,31,32,33,34]. Since switches used in the lab are not ideal, resistances of 90 Ω are connected in series with each ideal voltage-controlled switch in both of the topologies to make the simulation model more practical. Sizes of capacitors and resistors utilized at converter topologies are C 1 = C 2 = C 4 = 47 n F , C 3 = 2nf, RL = 10 KΩ, and V i n = 2 V .
Figure 6 and Table 2 show the simulation results of output voltage vs. clock frequencies for both topologies of boost converters. The novel topology of boost converter has a higher conversion rate than Makowski’s topology using the same number and size of capacitors.

3.2. Converter Lab Results

Makowski and the novel topologies of boost DC-DC converters were assembled on a RF bread board at the lab with CMOS switches (ALD 4213). Figure 7 and Table 3 show comparison between the two topologies of boost DC-DC converters for the lab results [35,36,37,38,39,40]. The novel topology for boost converter performs better conversion rate than Makowski’s topology between the bandwidth of switching frequency from 10 kHz to 150 kHz. Maximum conversion rate occurs at lower switching frequencies, whereas lower conversion rate occurs at higher switching frequencies. This is due to the fact that capacitors do not have enough time to be fully charged at high switching frequencies and the resistance of practical switches used in the lab.

4. Novel Topology of Boost Converter with Ferroelectric Capacitor

Ferroelectric capacitors with strontium bismuth tantalate (SBT) and lead zirconate titanate (PZT) materials have large dielectric constants, which increase their capacitance density [41,42,43,44,45]. In addition, polarization switching with applied voltage results in switching charge. Figure 8 introduces the polarization versus applied voltage hysteresis loop for the ferroelectric capacitors used in this work. Coercive voltage, Ec of the capacitor, is ±1 V, and spontaneous polarization is about 20 µC/cm2. Figure 9 presents topology of a novel boost converter with ferroelectric capacitor C 3 , which is developed using LTspice simulation software. Figure 10 shows the topology of the boost converter built at the lab for linear and nonlinear capacitors. To utilize switching polarization charge, voltage at the ferroelectric capacitor should be switched between +Vc and −Vc. Ref. [6], present method to apply the feature of switching reversal polarization at series and parallel boost converter by adjusting size of converter’s capacitors C 1 , C 2 ,   a n d   C 3   . The nonlinear capacitor, which is placed at C 3 , has to be scaled smaller than others so voltage across C 3 switches from positive during the first phase to negative during the second phase.
Figure 11 and Figure 12 present the output voltage results from both simulation and laboratory experiments for the novel topology utilizing linear and nonlinear capacitors alongside Makowski’s topology [46,47,48]. Those figures illustrate the scope of this paper, which is the improvement of conversion rate occurring to series and parallel topologies by reconfiguring their topologies using liner capacitors, as explained in detail earlier. To further increase the converter conversion rate, ferroelectric capacitors were used to utilize the feature of switching current. For simulation results at Figure 11, the novel topology with a nonlinear capacitor presents the highest conversion rate among other topologies. For experimental results at Figure 12, nonlinear capacitors present a high conversion rate at low switching frequencies. However, it presents poor performance at high switching frequencies due to voltage deficiency, which developed across a ferroelectric capacitor as a result of switches’ speed limitations, which are used in the lab.

5. Conclusions

In this paper, novel topologies for series and parallel boost DC-DC converters are developed to increase their conversion rate for the same number and size of capacitors. By reconfiguring Makowski’s topology, the novel topology shows better conversion rates at both simulation and laboratory experiments. Also, in this work, the utilization of nonlinear capacitors is presented to further increase the conversion rate of the boost converter by using the feature of switching current.
Some limitations and constraints appear to the novel topology of the boost converter, which limits its conversion rate. By reconfiguring the topology of the boost series and parallel converter, its conversion rate is going to increase only if four charge transfer capacitors are used. With fewer than four capacitors, the novel topology is going to show no superior conversion rate to Makowski’s topology. The other constraint appears by utilizing nonlinear capacitors, which require a complete cycle of switching voltage across ferroelectric capacitors for switching current to be utilized. However, due to the switches’ speed limit, a complete cycle of switching voltage does not occur, which makes no difference at conversion rate between linear and nonlinear capacitors applied to the novel topology of the boost DC-DC converter.

Author Contributions

Conceptualization, A.A. (Abdulaziz Alateeq); methodology, A.A. (Abdulaziz Alateeq); software, A.A. (Abdulaziz Alateeq); validation, Y.A.; formal analysis, A.A. (Ayoob Alateeq); investigation, Y.A.; resources, A.A. (Ayoob Alateeq); data curation, A.A. (Abdulaziz Alateeq); writing—original draft preparation, A.A. (Abdulaziz Alateeq); writing—review and editing, A.A. (Abdulaziz Alateeq); visualization, Y.A.; supervision, A.A. (Abdulaziz Alateeq); project administration, A.A. (Abdulaziz Alateeq); funding acquisition, A.A. (Ayoob Alateeq) and Y.A. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the Scientific Research Deanship at the University of Ha’il in Saudi Arabia through project number BA-2137.

Data Availability Statement

The original contributions presented in the study are included in the article, further inquiries can be directed to the corresponding author.

Acknowledgments

The authors of this paper would like to thank their sponsor, the Scientific Research Deanship at the University of Ha’il in Saudi Arabia, for their support throughout the project (project number BA-2137).

Conflicts of Interest

The authors declare no conflicts of interest.

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Figure 1. Makowsli’s topology of boost converter during (a) phase 1, (b) phase 2.
Figure 1. Makowsli’s topology of boost converter during (a) phase 1, (b) phase 2.
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Figure 2. The novel topology of boost converter during (a) phase 1 and (b) phase 2.
Figure 2. The novel topology of boost converter during (a) phase 1 and (b) phase 2.
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Figure 3. Switching capacitor converter with converter output impedance.
Figure 3. Switching capacitor converter with converter output impedance.
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Figure 4. Novel topology of boost DC-DC converter.
Figure 4. Novel topology of boost DC-DC converter.
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Figure 5. Hand calculation and simulation for the novel topology using linear capacitors simulation and experimental results.
Figure 5. Hand calculation and simulation for the novel topology using linear capacitors simulation and experimental results.
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Figure 6. Output voltage results for Makowski and the novel topologies at simulation.
Figure 6. Output voltage results for Makowski and the novel topologies at simulation.
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Figure 7. Output voltage results for Makowski and novel topologies at the lab.
Figure 7. Output voltage results for Makowski and novel topologies at the lab.
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Figure 8. Hysteresis loop for ferroelectric capacitor.
Figure 8. Hysteresis loop for ferroelectric capacitor.
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Figure 9. The novel topology of a boost converter with a nonlinear capacitor during (a) phase 1 and (b) phase 2.
Figure 9. The novel topology of a boost converter with a nonlinear capacitor during (a) phase 1 and (b) phase 2.
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Figure 10. The novel topology of a boost converter with a nonlinear capacitor built in the lab.
Figure 10. The novel topology of a boost converter with a nonlinear capacitor built in the lab.
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Figure 11. Simulation results for converter output voltage for Makowski’s topology, novel topology, and novel topology with nonlinear capacitors.
Figure 11. Simulation results for converter output voltage for Makowski’s topology, novel topology, and novel topology with nonlinear capacitors.
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Figure 12. Lab results for converter output voltage for Makowski’s topology, novel topology, and novel topology with nonlinear capacitors.
Figure 12. Lab results for converter output voltage for Makowski’s topology, novel topology, and novel topology with nonlinear capacitors.
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Table 1. Hand calculation and simulation for the novel topology using linear capacitors.
Table 1. Hand calculation and simulation for the novel topology using linear capacitors.
Clock Frequency (KHz)1030507090110130150
Calculation1.453.514.885.886.647.237.708.06
Simulation1.423.444.865.806.507.207.658.00
Table 2. Output voltage results for Makowski and novel topologies at simulation.
Table 2. Output voltage results for Makowski and novel topologies at simulation.
Clock Frequency (KHz)1030507090110130150
Makowski’s topology1.232.83.744.354.85.225.45.6
Novel topology 1.353.284.254.825.185.55.75.8
Percentage % 8.914.6129.757.335.15.263.44
Table 3. Output voltage results for Makowski and novel topologies at the lab.
Table 3. Output voltage results for Makowski and novel topologies at the lab.
Clock Frequency (KHz)1030507090110130150
Makowski’s topology1.292.893.84.384.785.055.235.34
Novel topology1.483.354.354.885.135.265.335.37
Percentage %12.813.712.610.26.841.870.55
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Alateeq, A.; Almalaq, Y.; Alateeq, A. Novel Topology for Modified Boost Series and Parallel Switching Capacitor DC-DC Converter. Electronics 2024, 13, 4439. https://doi.org/10.3390/electronics13224439

AMA Style

Alateeq A, Almalaq Y, Alateeq A. Novel Topology for Modified Boost Series and Parallel Switching Capacitor DC-DC Converter. Electronics. 2024; 13(22):4439. https://doi.org/10.3390/electronics13224439

Chicago/Turabian Style

Alateeq, Abdulaziz, Yasser Almalaq, and Ayoob Alateeq. 2024. "Novel Topology for Modified Boost Series and Parallel Switching Capacitor DC-DC Converter" Electronics 13, no. 22: 4439. https://doi.org/10.3390/electronics13224439

APA Style

Alateeq, A., Almalaq, Y., & Alateeq, A. (2024). Novel Topology for Modified Boost Series and Parallel Switching Capacitor DC-DC Converter. Electronics, 13(22), 4439. https://doi.org/10.3390/electronics13224439

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