Open AccessArticle

A CMOS Rail-to-Rail Class AB Second-Generation Voltage Conveyor and Its Application in a Relaxation Oscillator

Radivoje Djurić

and

Jelena Popović-Božović

Department of Electronics, School of Electrical Engineering, University of Belgrade, 11000 Belgrade, Serbia

Author to whom correspondence should be addressed.

Electronics 2024, 13(17), 3511; https://doi.org/10.3390/electronics13173511

Submission received: 4 August 2024 / Revised: 28 August 2024 / Accepted: 28 August 2024 / Published: 4 September 2024

(This article belongs to the Section Circuit and Signal Processing)

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Abstract

In this paper, we present a CMOS rail-to-rail second-generation voltage conveyor (VCII) suitable for low power applications, implemented in 180 nm CMOS technology with a supply voltage of ± 0.9 V. The proposed VCII consists of a current and voltage buffer operating in class AB. At the input of the voltage buffer, there is a bulk-driven differential amplifier, which provides a rail-to-rail input common-mode voltage. A common source output stage in class AB provides rail-to-rail at the output of the voltage buffer. The transistors are designed to operate in moderate inversion, achieving a relatively large current and voltage buffer bandwidth of 298.3 MHz and 173.2 MHz, respectively, with a power consumption of 157 μW. A sine wave with an amplitude of 1.5 V_pp and a frequency of 1 MHz on the output buffer has a total harmonic distortion of only 0.29%. The application of VCII in a relaxation oscillator with a frequency of up to 10 MHz is demonstrated, as well as its comparative characteristics with reference to other relevant square-wave generators published in the literature.

Keywords:

voltage conveyor; VCII; rail-to-rail; class AB; bulk-driven; low power; relaxation oscillator; negative impedance converter; negative resistance oscillator

1. Introduction

An analog building block (ABB) is a fundamental electronic circuit or component that performs an analog function. It is used in various applications, including signal processing, communication systems, control systems, and instrumentation. The most used ABBs are long-conceived operational amplifiers (OAs). However, designing low-voltage supply circuits with a high-gain bandwidth product and high current and voltage drive capability is challenging in modern technologies, so recently, other ABBs have been more frequently used. Current conveyors (CCs) are well-known wide-bandwidth blocks with current mode signal processing and simpler circuitry than OAs [1,2]. Voltage conveyors (VCs) were obtained by swapping input and output stages in a CC [3,4,5,6,7], which resulted in an ABB with an input current buffer (CB) and an output voltage buffer (VB).

The VCII is an ABB with a low-impedance current input port (Y), a high-impedance current output port (X), and a low-impedance voltage output port (Z). Like a second-generation current conveyor (CCII), the VCII is versatile and can be configured in various ways to achieve different functions in a wide frequency range. However, it has an output voltage buffer, unlike CCII, so it is more suitable in circuits with low load impedance and high output current. Therefore, it is not necessarily an additional output voltage buffer as with the CCII-based circuits, so lower power consumption and a smaller chip area can be expected. Another important feature of the VCII is the ability to use the Y port as both current and voltage input because its input impedance can be very low [8,9,10]. The VCII processes the input current at the Y port, and due to the low impedance (practically grounded), a voltage can easily be applied via the series resistance (V/I conversion). This feature also allows simple implementations of current summing/subtracting operations at the Y port, and an additional advantage is the possibility of programmable control of the parasitic Y impedance [11,12,13,14]. Voltage conveyors are specifically designed to handle and transfer voltage signals directly, so signal processing operations, such as voltage amplifiers, typically require fewer active blocks than CCII-based ones [15,16]. During the past decade, the VCII has attracted the attention of researchers. Its various applications have been presented in positive and negative impedance simulators and impedance multipliers [8,11,15,17,18,19,20,21], different types of analog filters [12,13,22,23,24], voltage amplifiers [25,26,27,28], sinusoidal oscillators [29,30], the Schmitt Trigger [31,32], electronic interfaces for biosensors [33,34], etc. Since a literature survey has shown that realizations of relaxation oscillators with a VCII based on a negative impedance converter (NIC) have not yet been published, we have decided to investigate them. Like a CCII, a VCII provides high linearity and stability, which are useful in relaxation oscillators. This ensures that the oscillation frequency remains stable during the process, supplying voltage and temperature (PVT) variations. The wide bandwidth allows them to design square-wave oscillators with tunable frequencies by modifying passive components such as resistors and capacitors. A CCII is preferred in high-frequency current-mode oscillators, while a VCII is suitable for both oscillator types, whether current- or voltage-mode.

For increased efficiency, more efficient methods must be used, both statically and dynamically, which will polarize the output stage in class B or AB. Class B has the highest efficiency but also large crossover distortions and a difficult adjustment of open loop quiescent operating points. Class AB provides the possibility of obtaining high efficiency with relatively low distortion. A large voltage or current is required when there is a large output power load, either static or dynamic. Advanced CMOS technologies usually have low supply voltages, so the need for a large output swing is more pronounced. The output of VCII is VB, so a large input and output swing must be provided simultaneously. A more efficient CB is obtained when operating in class AB for the same reasons as the VB. Analyzing previously reported VCII implementations, it was noted that several circuits were designed in class AB [9,16,35,36,37,38,39], and some had very simple realizations [16,36,38]. The VCII described in [16] has very large current and voltage transfer bandwidths, but the current/voltage offset is significant. The other circuits are designed for low-voltage low-power applications but suffer from high input impedances at current inputs [36] or operate efficiently for relatively low frequencies [38]. Many reported realizations of class AB VCIIs are not rail-to-rail [9,16,37,39].

In this paper, we propose a VCII operating in class AB to reduce power consumption that has rail-to-rail input and output capability. Designing low-voltage supply circuits with high current and voltage drive capabilities is challenging. The design process of the proposed VCII includes several constraints: the higher the bandwidth, the lower the dissipation, and the smaller the area of the integrated CMOS realization. Moderate inversion was chosen as a compromise for transistor design. A negative feedback loop was applied to obtain a low impedance at the Y and Z terminals. It makes implementation more complex but provides a higher bandwidth and robustness to PVT variations. Current and voltage buffers are designed in class AB due to symmetry, high slew rate, and low dissipation. Because of the rail-to-rail requirement, simple current sink/source and common source transistors on their outputs were used. A folded cascode differential amplifier, which has a large power supply rejection ratio (PSRR), was used in the VB input stage.

A designed VCII was used to realize a NIC as an active part of the relaxation oscillator. Using rail-to-rail VCII, an oscillator with low phase noise is obtained [40]. The key VCII performances decisive for designing an oscillator are power dissipation, harmonic distortion, bandwidth, and port characteristic impedances. Since the short-channel transistor models are non-linear, the initial design provides rough estimates of the VCII characteristics. Iterative simulations are used to first adjust the operating point parameters, then the dynamic characteristics of the VCII, and finally, the assessment of deviations due to PVT variations.

The realization of a new CMOS rail-to-rail class AB second-generation voltage conveyor is described in Section 2. Simulation results for the proposed circuit and comparison with other reported class AB rail-to-rail VCII realizations are also presented in this section. The analysis of a relaxation oscillator based on a voltage conveyor is presented in Section 3. In this section, an approximate alternative determination of the oscillation frequency of an oscillator with negative resistance, its change due to PVT variations, Monte Carlo analysis, and phase noise are also given. All circuits are simulated in 180 nm CMOS integrated technology, and a supply voltage of ±0.9 V was used using the Cadence IC design package. Simulation results obtained by DC, AC, and transient simulations, as well as periodic steady state (PSS), phase noise, and s-parameter analysis, are given. Section 4 concludes this paper by comparing the proposed relaxation oscillator with a VCII and several other relevant oscillators.

2. Class AB Rail-to-Rail VCII

The second-generation voltage conveyor is a three-terminal element defined by the following relations [15]:

[\begin{matrix} i_{X} \\ v_{Y} \\ v_{Z} \end{matrix}] = [\begin{matrix} \frac{1}{r_{X}} + s C_{X} & β & 0 \\ 0 & r_{Y} + s L_{Y} & 0 \\ α & 0 & r_{Z} + s L_{Z} \end{matrix}] [\begin{matrix} v_{X} \\ i_{Y} \\ i_{Z} \end{matrix}],

(1)

where

α

is the voltage gain between X and Z terminals,

β

is the current gain between Y and X terminals, and

r_{X}

C_{X}

r_{Y}

L_{Y}

r_{Z}

, and

L_{Z}

are elements of parasitic impedances associated with terminals (Figure 1). In an ideal case, all parasitic impedances could be neglected and both gains are unitary,

α = 1

β = 1

. The sign of current gain

β

determines the type of VCII: positive

({VCII}^{+})

for positive

β

(ideally

β = + 1

) or negative

({VCII}^{-})

(ideally

β = - 1

). As we shall see later, negative-type VCII will be necessary to implement a single VCII relaxation oscillator for the same reasons as shown for single VCII sinusoidal oscillators [29].

The three-terminal element defined by (1) can be realized as a cascade connection of a current buffer (CB) as the input block and a voltage buffer (VB) as the output block (Figure 2) [5].

2.1. The Class AB Current Buffer

The CB of the proposed VCII operates in class AB and is shown in Figure 3 [32]. Transistors

M_{1} - M_{4}

form a translinear loop, while transistors

M_{5} - M_{6}

create the negative feedback that decreases the input impedance of the CB. Transistors

M_{9} - M_{12}

are added to the circuit to invert the CB characteristic to obtain a

{VCII}^{-}

, a negative type of voltage conveyor. When

i_{Y} = 0

M_{5}

and

M_{6}

conduct approximately

I_{B 1}

and the output current is

i_{X} = 0

. As the input current

i_{Y}

increases, the drain current

i_{D 6}

increases, while the current

i_{D 5}

decreases until

M_{5}

is cut off, as well as

M_{7}

M_{9}

M_{12}

, and

M_{14}

. It is similar to the following: current

i_{Y}

decreases; the transistor

M_{6}

is cut off, as are

M_{8}

M_{10}

M_{11}

, and

M_{13}

. Since

M_{1}

and

M_{2}

have a constant drain current and work in the saturation, mapping the current through the current mirrors, an expression for the idealized current gain of the CB is easily obtained:

β = \frac{i_{x}}{i_{y}} = - 1

(2)

The input resistance at the quiescent point is:

r_{Y} = r_{Y - u p} | | r_{Y - d n} \approx \frac{1}{g_{m 3} g_{m 5} r_{d s 3}} | | \frac{1}{g_{m 4} g_{m 6} r_{d s 4}},

(3)

where

r_{Y - u p}

and

r_{Y - d n}

are the input resistances of the upper and lower parts of the buffer, respectively. Transconductances

g_{m 1}

and

g_{m 2}

affect the

r_{Y}

when the output resistances of the current sources

I_{B 1, b, d}

are small. Their influence can be neglected when

g_{m 1} R_{o u t 1, b} ≫ 1

and

g_{m 2} R_{o u t 1, d} ≫ 1

, where

R_{o u t 1, b}

and

R_{o u t 1, d}

are the output resistances of current sources

I_{B 1, b}

and

I_{B 1, d}

, respectively. The products

g_{m 3} r_{d s 3}

and

g_{m 4} r_{d s 4}

are the intrinsic transistor gains, which are simultaneously the loop gain of the CB. When they are high, the resistance at the Y port tends to zero.

The output resistance of the CB at the quiescent point is:

r_{X} = r_{d s 13} | | r_{d s 14} = \frac{1}{g_{d s 13} + g_{d s 14}} .

(4)

The dimensioning of the CB transistor results from the compromise for a low quiescent current, the largest bandwidth, the slightest influence of technological parameters, and the largest output voltage swing. A large

g_{m} / I_{D}

means low power dissipation and a large output swing, while a small

g_{m} / I_{D}

provides a larger bandwidth and a faster response [41]. Therefore, the operating points of all transistors are set for moderate inversion.

The transistor channel length was chosen to reduce the influence of the Early effect and provide a suitable bandwidth. Current sources

I_{B 1, a} = I_{B 1, b} = I_{B 1, c} = I_{B 1, d} = 5 μ A

are implemented using NMOS (

I_{B 1, c}, I_{B 1, d}

) and PMOS (

I_{B 1, a}, I_{B 1, b}

) current mirrors with transistors whose dimensions are

4.32 μ m / 0.54 μ m

and

12.96 μ m / 0.54 μ m

, respectively. In the current mirrors, transistors with

L = 3 L_{\min} = 0.54 μ m

were used to reduce the Early (

λ

) effect and provide high output resistance. All other transistors have a channel length

L = 0.36 μ m

, while Table 1 lists the channel widths and their

g_{m} / I_{D}

parameters.

Figure 4 shows the Y−X transfer function when the X terminal is connected to the ground. The same Figure also shows the

β

coefficient, which was obtained using the derivative of the transfer function.

When transistors

M_{5}

and

M_{6}

conduct the same current, the current gain

β_{D C}

has a minimum value

β_{D C \min} = - 1.119

, and increases with the increasing absolute value of the current

i_{Y}

. The absolute value of the current gain is higher than 1 due to the Early effect in the current mirrors

M_{7} - M_{14}

To investigate the current buffer time-domain behavior, a 1 MHz sine wave with a parametric amplitude

I_{m}

was applied to the Y terminal. By determining the short-circuit current of the X terminal in the time domain, total harmonic distortions (THDs) as a function of the amplitude

I_{m}

are obtained (Figure 5). At a low input current amplitude

I_{m}

, all CB transistors are conducted in class A, which has a limited current drive capability at the X port. When the

I_{m}

is high, transistor

M_{13}

drives port X practically half the time, with the other half driven by

M_{14}

, and the quiescent current is the same as in class A. The benefits of driving in class AB are that significantly higher currents than bias currents are possible at port X, but at the cost of increased distortions. Therefore, the power dissipation is low, the efficiency is relatively high, and high currents can be achieved to drive the X capacitive load.

2.2. The Rail-to-Rail Voltage Buffer

The proposed voltage buffer is shown in Figure 6. It consists of an input folded-cascode amplifier (

M_{15} - M_{22}

) and a simple rail-to-rail common source output stage with class AB control (

M_{23} - M_{25}

). Because of the high gain of the output stage VB, the gate voltage of

M_{23}

changes slightly as the output voltage changes, so all transistors in the rail-to-rail range will be saturated. It is well-known that the input common-mode voltage can be close to the negative power supply using a standard PMOS folded-cascode amplifier. The limitation of the input common-mode voltage from the upper side is that the transistor in the current source goes into the triode region.

Standard gate-driving differential amplifiers often use complementary input pairs (NMOS and PMOS) to cover the entire rail-to-rail input range [35,42]. The NMOS pair operates effectively when the input voltage is close to

V_{S S}

, while the PMOS pair is active when the input voltage is close to

V_{D D}

. Together, they ensure continuous operation across the entire input range. The design ensures a smooth transition between the NMOS and PMOS input pairs as the input voltage varies, preventing any dead zones or significant drops in performance across the input range. In low-voltage designs, the input can maintain operation across rail-to-rail input voltage by driving the bulk instead of the gate. Choosing a suitable voltage on the drain of the transistors

M_{15}

and

M_{16}

, approximately

- 550 mV

, it is ensured that within

- 0.9 V \leq V_{C M} \leq 0.9 V

, it cannot forward-bias the bulk-source and bulk-drain junctions in the PMOS structure [43,44]. If the input

V_{C M}

increases in the rail-to-rail range, the voltage on the source-coupled pair

V_{S 15, 16}

also increases. Due to the nonlinear characteristics

i_{D} = f (v_{G S}, v_{B S}, v_{D S})

, the change is smaller, approximately in the range of

- 0.5 V \leq V_{S 15, 16} \leq - 0.1 V

. When the

V_{C M} \leq - 400 mV

, the body-source junction becomes forward-biased, but not enough to disturb the operation of transistors

M_{15} - M_{16}

in the inversion region. Then, the input leakage currents are in the order of pA, similar to in [44].

Although its transconductance is significantly lower than when the excitation is applied to the gates, the DC voltage gain of the folded cascode amplifier is large, primarily due to the large output resistance. The output pole, determined by output capacitance and resistance, determines its frequency response.

The class AB output stage is implemented using the translinear contour

M_{23} - M_{25}

[45]. The output transistors are in common-source configuration and have a large voltage gain whether they conduct both

M_{24}

and

M_{25}

, or just one of them. Because of capacitances

C_{g d 24}

and

C_{g d 25}

, the transfer function of the VB output stage has a right half-plane zero, so additional compensation is necessary to ensure a satisfactory phase margin when closing the feedback loop. This was achieved with the compensation capacitor

C_{C}

, using Miller compensation. We obtain approximately a single pole transfer function with it, but a new left half-plane zero also occurs. To reduce its influence,

C_{C}

is connected to the source

M_{20}

, which has a low input resistance instead of the gate

M_{23}

According to the circuit configuration, the input impedance is predominantly capacitive, while the output impedance can be equivalent to a series connection of resistance and inductance. The output resistance of the voltage buffer can be obtained by applying Blackman’s theorem [46]:

r_{Z} = \frac{1}{g_{m b 15, 16} R_{o u t 1} \cdot (g_{m 24} + g_{m 25})},

(5)

where

g_{m b 15, 16}

is the body transconductance of

M_{15, 16}

, while

R_{o u t 1}

is the output resistance of the first stage of the voltage buffer:

R_{o u t 1} = g_{m 20} r_{d s 20} r_{d s 22} | | g_{m 18} r_{d s 18} r_{d s 16} .

(6)

The DC open-loop voltage gain is large:

A_{0} = g_{m b 15, 16} R_{o u t 1} \cdot \frac{g_{m 24} + g_{m 25}}{g_{d s 24} + g_{d s 25}},

(7)

so the DC voltage gain of the VB is:

α = \frac{v_{z}}{v_{x}} = \frac{A_{0}}{1 + A_{0}} \approx 1 .

(8)

The design of the VB is based on the same principles as that of the CB. All transistors have the same channel length

L = 0.36 μ m

, while their channel widths and

g_{m} / I_{D}

coefficients are given in Table 2.

Current source

I_{B 2} = 10 μ A

is implemented using a PMOS current mirror with

W / L = 25.92 μ m / 0.54 μ m

. The NMOS current mirror, with (W/L) of

12.96 μ m / 0.54 μ m

and

4.32 μ m / 0.54 μ m

, has been used in current sources

I_{B 3, a} = I_{B 3, b} = 15 μ A

and

I_{B 4} = 5 μ A

, respectively.

When the terminal Z is loaded with the resistance

R_{L} = 10 k Ω

, the VB voltage transfer function and its derivative are shown in Figure 7. Extremely good linearity of the VB is observed, and at

V_{X} = 0

, the voltage gain is

α = 0.9994

. Distortion occurs if the voltage gain (α) is not uniform across the rail-to-rail input range. When the change is symmetrical concerning the operating point, the output voltage will not contain even harmonics, and a more significant deviation from unity leads to a stronger influence of odd harmonics and THD increases. When a complex periodic voltage appears at the input of the VB, as is the case in relaxation oscillators, intermodulation distortions occur.

2.3. Simulation Results for VCII

Nominal values of VCII parameters at the quiescent point with

V_{D D} = - V_{S S} = 0.9 V

and

C_{C} = 65 fF

were obtained by simulation:

V_{Y D C} = 2.23 μ V

V_{X D C} = 15.34 μ V

V_{Z D C} = - 189.3 μ V

r_{Y} = 110.4 Ω

L_{Y} = 2.1 μ H

r_{X} = 759.7 k Ω

C_{X} = 41.95 fF

r_{Z} = 4.86 Ω

, and

L_{Z} = 1.73 μ H

. The circuit power consumption was

157 μ W

. Voltage deviation from zero values on individual VCII terminals represents voltage offset. Due to the DC-negative feedback in the CB and the VB, the voltage offset is small at the Y and Z terminals. Adjusting the geometries of the transistors in the current buffer obtained a small voltage offset at the X terminal.

For the sake of comparison to the results from other works [37], the terminal Z is loaded with a parallel connection of capacitance

C_{L} = 1 pF

and resistance

R_{L} = 10 k Ω

. Figure 8 shows the transfer functions of the CB (

β

) and the VB (

α

). The DC gains of the current and the voltage buffer are

β_{0} = 975.5 mdB

and

α_{0} = - 4.75 mdB

, while the 3 dB bandwidths are

β_{B W} = 298.3 MHz

and

α_{B W} = 173.2 MHz

1 MHz

sine wave with a maximum peak amplitude of

1.5 V

was applied to the VB input. Using PSS analysis, the THD value with 10 harmonics was found to be 0.29%.

By determining the response to rectangular voltage excitation, it is obtained that the slew rate of the voltage buffer is

S R^{+} = 173.8 V / μ s

and

S R^{-} = 146.3 V / μ s

. At a small fast change of excitation, the settling times in CB and VB are obtained. With capacitive load

C_{L} = 1 pF

, at

R_{L} = 10 k Ω

and

R_{L} \to \infty

, VB settling times are

t_{s α 1} = 11.9 ns

and

t_{s α 2} = 15.1 ns

, respectively. The CB settling time is also small,

t_{s β} = 3.1 ns

Variations in the process, supply voltage, and temperature have been investigated through PVT corner analysis, considering a ±10% variation at the power supply for temperatures of −20 °C, 25 °C, and 80 °C (shown in Table 3).

Table 3 shows that the

α

and

β

parameters are robust, while the series resistance

r_{Z}

and inductance

L_{Z}

change the most. It is a consequence of the dependence of the quiescent current of the VB output stage on the supply voltage.

The nominal inductive reactances of the Y and Z terminals at 1 MHz are

X_{L Y} = 2 π f L_{Y} = 13 Ω

and

X_{L Z} = 2 π f L_{Z} = 11 Ω

, respectively. Comparing these values with the resistances

r_{Y}

and

r_{Z}

, it is concluded that series inductance has very little effect on the Y input, while its effect on the Z output is large. Even so, the impedance of the Z output is relatively small, as a magnitude of 50 Ω is reached at about 4.5 MHz.

At the minimum supply voltage of

\pm 0.81 V

, distortions

T H D_{X - Z}

increase due to clipping the sine wave at the output.

Table 4 shows the results of the Monte Carlo simulation on 500 samples. It can be seen from this Table that VCII is quite immune to the statistical variation of the parameters.

Table 5 shows the characteristics of the relevant published VCII. Due to the channel-length modulation effect (λ effect) in the current mirrors

M_{7} - M_{14}

, the CB

{VCII}^{-}

distortions are relatively large. When longer channels are used, these distortions are smaller, but the CB bandwidth is lower. The channel length

2 L_{\min} = 0.36 μ m

was selected as a compromise in the proposed CB design. When

M_{11} - M_{14}

are removed from the circuit and the drains

M_{9}

and

M_{10}

are shorted to the output, the

V C I I^{+}

current buffer is obtained. To obtain a small offset of CB

V C I I^{+}

, the channel width

M_{2, 4, 6}

should be

W_{2, 4, 6} = 11.77 μ m

. Its current gain is slightly higher than one,

α = 1.044

, but it is much more linear. When the Y input has the same excitation as the CB

{VCII}^{-}

, at a current of

2 {mA}_{pp}

, a THD of 1% is obtained. In the simulation, the offset voltage of the X port is

V_{X D C} = 6.64 μ V

, and other

V C I I^{+}

parameters are shown in Table 5. Compared to this, only reference [37] has a better linearity. In that VCII, a λ effect cancellation circuit was used to obtain a more linear CB at the cost of increased power dissipation.

References [35,38] have lower power dissipation than the proposed VCII. When the class A CB and the class AB VB are supplied from the same voltage,

\pm 0.9 V

, the VB in [38] is not rail-to-rail. Rail-to-rail functionality is obtained using a charge pump that increases the supply voltage of the output stage, and additional drivers are needed. The bandwidth of the proposed VB is slightly lower than in [38], while the bandwidth of the CB is significantly higher. In [35], CB and VB are rail-to-rail and class AB, and VB has two complementary differential amplifiers at the input. The differential amplifiers are switched on depending on the VCM voltage. The proposed VCII has slightly higher power dissipation but much higher bandwidth on both VCII stages.

Of all referenced VCIIs, reference [32] has the lowest consumption of only 38 uW. That

V C I I^{-}

consists of a class AB CB and a push-pull class B VB, has a

\pm 1.65 V

power supply, and is part of a Schmitt Trigger. Due to the lack of other relevant parameters, the comparison with it in Table 5 is omitted.

Compared to other reference works, the proposed VCII has the best VB linearity, the highest input resistance at the X terminal, and the smallest sum of series resistances at the Y and the Z terminals. It also has a relatively low power consumption. The disadvantage of the proposed solution is a relatively low linearity of the CB

{VCII}^{-}

, which is a consequence of implementing

{VCII}^{-}

by cascading current mirrors to invert the current.

3. Proposed Relaxation Oscillator with VCII⁻

A new VCII application, an implementation of a NIC-based relaxation oscillator, will be presented. Voltage conveyors can be used to perform the function of a NIC. The voltage-driven NIC is already used in some applications, for example, in VCII-based grounded C multiplier circuits with negative multiplication factors [8]. For the implementation of relaxation RC oscillators, NIC static characteristics should be uniquely defined for the current that controls the operation of the oscillator [47].

3.1. Circuit Description and Equivalent Model

Figure 9 shows a realization of current-driven NIC implemented with

{VCII}^{-}

. Since the voltage at the X terminal is

v_{X} = - Z_{X} \cdot i_{X}

and, according to (1), an ideal case is

i_{X} = - i_{Y}

v_{Z} = v_{X}

v_{Y} = 0

, the input impedance between the Z and Y terminals is:

Z_{i n} = \frac{v_{Z} - v_{Y}}{i_{I N}} = \frac{v_{X}}{- i_{Y}} = - Z_{X} .

(9)

At low frequencies, the parasitic impedance at terminal X is resistance

r_{X}

, which means that the equivalent impedance is negative

Z_{i n} = - r_{X}

, even without additional impedance at terminal X. This means that the NIC static characteristic around the coordinate origin has an inherently high negative resistance (Equation (4)), which is a very useful feature for the implementation of the active part of an oscillator since it ensures the reliable startup of oscillations. As we shall see later, for large absolute values of control current, NIC static characteristics have positive slopes because some transistors will be cut off.

A schematic diagram of the proposed relaxation oscillator based on a

{VCII}^{-}

is shown in Figure 10a. Because of the small Y impedance, the output voltage is simply converted into current, and the output voltage buffer allows it to easily drive an external load. The active part of the oscillator is a current-driven NIC with current-voltage characteristic

v = f (i)

, which can be approximated by three linear segments, see Figure 10b. To better control the shape of the static characteristic of the NIC, we added a serial resistor

R_{F}

. The network of the oscillator contains a capacitor, but in the model, we have included the parasitic inductance at the Y or the Z terminal to explain fast current changes in the further analysis of the relaxation oscillator. The typical role of inductance is hindering abrupt current changes, but if we have a small inductance (

L_{Z} \to 0

), it allows very fast current changes (

d i_{L_{Z}} / d t \to \infty

) [48], i.e., the “jump” of current i in the relaxation oscillator in Figure 10a. For the sake of simplicity of analysis, the other parasitic elements can be ignored. This model and analysis are very similar to those of the relaxation oscillator based on the CCII described in [40], so they will be repeated in this paper briefly.

Using the notation from Figure 10a, the behavior of this circuit can be described as:

\frac{d i}{d t} = - \frac{1}{L_{Z}} f (i) + \frac{1}{L_{Z}} v_{C},

(10)

\frac{d v_{C}}{d t} = - \frac{1}{C} i .

(11)

Since the quiescent point of this circuit is at the coordinate origin where the characteristic

f (i)

can be approximated by

R_{I I} = - R_{n}

, the real part of the characteristic equation solution is positive for

R_{n}, L_{Z} > 0

[47]. Thus, it can be concluded that the oscillation startup in this oscillator is always reliable and does not depend on the value of the capacitance in the timing network. It is assumed that the negative slope segment on NIC characteristics exists. If the condition:

R_{n} > \sqrt{\frac{4 L_{Z}}{C}}

(12)

is fulfilled, the characteristic equation solutions are real and positive, and the operating point is moving along a linear trajectory from the coordinate origin until the point where the current is limited by the NIC static characteristic. The limit cycle of the oscillator is almost immediately reached in the first period, and there is a direct oscillation startup. This behavior is typical of the relaxation oscillators, and it can be achieved for large values of

C

. If condition (12) is not fulfilled, the solutions are conjunctive-complex, and the limit cycle will be set up after several periods of oscillation [47]. In that case, the circuit behaves as a nearly sinusoidal oscillator, so we will not analyze it in this paper.

To determine

R_{n}

, i.e., the equivalent resistance seen by the capacitor

C

at the quiescent operating point, we will use the circuit based on the VCII model for small signals at low frequencies (Figure 11). If we assume that the X terminal is unloaded, from the equations:

v_{t} = v_{t}^{+} - v_{t}^{-} = α v_{X} + r_{Z} i_{t} + (r_{Y} + R_{F}) i_{t},

(13)

v_{X} = - β i_{Y} r_{X} = β r_{X} i_{t}, R_{X} \to \infty,

(14)

we obtain the equivalent resistance

R_{t} = v_{t} / i_{t} = α β r_{X} + r_{Y} + r_{Z} + R_{F} .

(15)

This resistance can be negative if we use a negative type VCII (

β < 0

), and the following condition is fulfilled:

|α β r_{X}| > r_{Y} + r_{Z} + R_{F} .

(16)

Since

r_{X}

is the high output resistance of CB, both gains are approximately equal to unity and

r_{Y}, r_{Z}

are low resistances (Table 5). This condition is easy to fulfill even for relatively high resistance

R_{F}

. According to the markings in Figure 10b and this analysis, the slope of segment II with negative resistivity is:

R_{I I} = r_{Y} + r_{Z} + R_{F} - |α β r_{X}| \approx R_{F} - r_{X} .

(17)

However,

R_{F}

affects other characteristics of the oscillator, so the slope with negative resistance can be independently adjusted by external resistance

R_{X}

(Figure 11). In that case,

r_{X}

should be replaced with

r_{X} | | R_{X}

in the previous analysis.

3.2. Estimation of the Oscillation Period

The period of oscillations is equal to the time needed for the operating point to go once through the limit cycle. It is a characteristic of relaxation oscillators that the operating point has “slow” and “fast” motions during the limit cycle. When the operating point reaches the circuit’s static characteristics at the beginning, it continues in “slow” motion on the positive slope segment until the breaking point of that segment. After that, it has to “jump” to the other positive slope segment of the static characteristics. This means that there is an instant current change controlling the oscillator operation while the voltage is constant. The current “jump” is made possible by the parasitic inductance

L_{Z}

of a small value, and the voltage is kept constant by capacitance

C

. We can consider that these jumps are instantaneous and neglect them in the calculations of the period of oscillations. Thus, the period of oscillations is the time when the operating point is on segments I and III of the characteristics shown in Figure 10b:

T = \oint_{c} d t \approx Δ t_{I} + Δ t_{I I I} .

(18)

For the analysis of slow motions, the parasitic element can be ignored,

L_{Z} = 0

, and the static characteristic can be approximated as

f (i) = R_{I} \cdot i

f (i) = R_{I I I} \cdot i

. Under these assumptions, from (11) and (18), the period of oscillation can be easily calculated:

T = C R_{I} \ln \frac{I_{1}}{I_{2}} + C R_{I I I} \ln \frac{I_{3}}{I_{4}} .

(19)

The period depends on the capacitance

C

and the shape of the NIC static characteristic: the slope of segments I and III and the location of the turning points [47]. To simplify the analysis, we can assume that the characteristic is symmetrical, and the slopes of these segments are equal,

R_{I} = R_{I I I}

. In that case,

V_{1} = - V_{2}

I_{2} = - I_{4}

I_{1} = - I_{3}

and:

\frac{I_{1}}{I_{2}} = \frac{I_{3}}{I_{4}} = \frac{R_{I I I} - 2 R_{I I}}{R_{I I I}} .

(20)

According to (19), the oscillation period is:

T = 2 C R_{I I I} \ln \frac{I_{3}}{I_{4}} = 2 C R_{I I I} \ln \frac{R_{I I I} - 2 R_{I I}}{R_{I I I}} .

(21)

3.3. Analysis and Design of the Proposed Relaxation Oscillator

In the steady-state oscillation process, due to the rail-to-rail feature, the maximum and the minimum VB output voltages are approximately

V_{D D}

and

V_{S S}

, respectively. For the initial observation time, we will take the state when the output Z has a minimum voltage. Then, there is also a low voltage on the X terminal and the transistor

M_{14}

is in the triode region. The current

i_{Y}

, which is simultaneously the current of the capacitor

C

, increases, as does the current

- i_{X}

. When the current

i_{X}

reaches the value that drives

M_{14}

out of the triode region, both

M_{13}

and

M_{14}

are in saturation, a positive feedback loop is established in the circuit that drives

M_{13}

into the triode region, and the output Z goes from a low to a high voltage level. The voltage on the capacitor

C

cannot be changed instantaneously, so this fast change in the voltage

v_{Z}

causes a fast change in the current

i_{Y}

, after which the current falls exponentially until

M_{13}

exits the triode region. Then, again, both

M_{13}

and

M_{14}

are in saturation, so due to the strong positive feedback, the voltage at the X terminal drops sharply from a high to a low voltage level, driving the transistor

M_{14}

into the triode region and fast-changing the voltage

v_{Z}

from a high to a low voltage level. The current

i_{Y}

has a steep downward change and then rises exponentially until it reaches a threshold that again drives the transistor

M_{14}

out of the triode region, thus ending one period of the steady-state operation.

Figure 12 shows the periodic steady-state diagrams of the voltage

v_{Z}

and

v_{X}

, as well as the current

i_{Y}

in the oscillator with

V_{D D} = - V_{S S} = 0.9 V

R_{F} = 22 k Ω

, and

C = 6.5 pF

To adjust the shape of the static characteristic of the active part of the oscillator, we need to determine the slope of the segments with positive resistivity (segments I and III in Figure 10b). In these areas, the output Z is in voltage saturation, so the slopes of these segments are:

R_{I} = R_{I I I} = r_{Y} + r_{Z s a t} + R_{F},

(22)

where

r_{Z s a t}

is the output resistance of the saturated output Z. Note that

R_{F}

affects these slopes. We previously determined the expression for the negative slope on segment II (Equation (17)) and explained the effects of resistances

R_{F}

and

R_{X}

Figure 13 shows the resistance seen by the capacitor C for two feedback resistances,

R_{F 1} = 10 k Ω

and

R_{F 2} = 22 k Ω

, and two external resistances,

R_{X} = 100 k Ω

and

R_{X} \to \infty

. The slope in segment II must be negative, and this will be fulfilled when it is

R_{F 1, 2} < r_{X} | | R_{X}

. Because of the large CB output resistance

r_{X}

, the slope in segment II changes slightly with the change in

R_{F}

Assuming

r_{Y}, r_{Z}, r_{Z s a t} < < R_{F}

and combining (17), (21), and (22), the oscillation period for circuits with unloaded X terminal is:

T = 2 C R_{I I I} \ln \frac{R_{I I I} - 2 R_{I I}}{R_{I I I}} \approx 2 C R_{F} \ln (\frac{2 |α β r_{x}|}{R_{F}} - 1) .

(23)

With external resistance

R_{X}

, the oscillation period is:

T \approx 2 C R_{F} \ln (\frac{2 |α β (r_{x} | | R_{X})|}{R_{F}} - 1),

(24)

and in the idealized case,

α = 1

and

β = - 1

become:

T \approx 2 C R_{F} \ln (\frac{2 (r_{x} | | R_{X})}{R_{F}} - 1) .

(25)

Due to extra resistance

R_{X}

, the oscillation frequency can be adjusted better, thus making the oscillator more robust to PVT variations. The same expression for the frequency of the idealized relaxation oscillator

(r_{X} \to \infty)

, but in a different way, was obtained in reference [49].

The first step in relaxation oscillator design is to ensure the oscillations start. According to (16) and the VCII parameters shown in Table 5, we have chosen

R_{F} = 22 k Ω

and

R_{X} = 100 k Ω

. Since

R_{F}

determines the slope of positive segments of the static characteristic, i.e., determines the location of the turning points (Figure 10b), with the chosen value, we limited the current to approximately 70 µA. Finally, choosing the capacitance

C

, the oscillation frequency

f_{0}

can be determined according to (25). For example, for

C = 11.5 pF

, the estimated operating frequency is 1.013 MHz, while it is 1.049 MHz when simulated.

The dependence

f_{0}

as a function of the capacitance

C

is shown in Figure 14. The same picture shows the specified dependency obtained by simulation and the dependence of the relative error of the frequency estimation on the frequency.

The simplified Formula (25) for determining the oscillation frequency shows good agreement with simulations, as shown in Figure 14. At low frequencies, the relative error has an offset because of the influence of parasitic series resistances. As the frequency is increased, hysteresis appears in the controlled impedance

v = f (i)

. As Figure 15 shows, the width of hysteresis increases when the working frequency increases. Neglecting the transition time yields a simplified expression for the oscillation period. With increasing frequency, the time that the oscillator spends in the zone with negative impedance is no longer negligible, and the frequency decreases to the idealized characteristic. This is mostly due to the influence of the Y and Z inductive reactances, which decrease the rate of change of the capacitor current when the oscillator switches from one state to another.

To decrease the CB distortion,

R_{F}

is adjusted to limit the maximum current of the Y input. The series inductances

L_{Y}

and

L_{Z}

additionally limit the fast-change

i_{Y}

and thus the CB distortion.

Figure 16a shows the periodic steady-state diagrams of the voltage

v_{Z}

and

v_{X}

and the current

i_{Y}

when

C = 0.79 pF

, while other parameters are unchanged, being

R_{F} = 22 k Ω

and

R_{X} = 100 k Ω

. This sets the oscillation frequency to 10 MHz. The rise and fall times of the current

i_{Y}

, when the oscillator switches from one state to another, are determined from the

i_{Y}

diagram as

t_{r} \approx t_{f} = 12.5 ns

. When these times are added to the idealized charging and discharging times, the estimated (24) and simulated frequencies are approximately the same. Figure 16b shows the dependence of the voltage on the capacitor as a function of the capacitor current at the oscillation frequency, that is, the phase portrait of the oscillator at 10 MHz. It is observed that the oscillator enters the steady state after one period of oscillation.

In transition mode, when the supply voltage reaches ±0.5 V, the oscillations begin to establish and reach their final amplitude at ±0.9 V. When the solutions of the characteristic equation are real and positive (condition (12)), i.e., for the relaxation type of oscillations, the startup time is approximately equal to one oscillation period (Figure 16b). If the solutions of the characteristic equation are conjunctive-complex, the startup time is several periods (we did not analyze it in this paper because it is a nearly sinusoidal oscillator).

3.4. Simulation Results for the Relaxation Oscillator

Table 6 shows the oscillating frequency after standard PVT variation in the oscillator with

R_{F} = 22 k Ω

R_{X} = 100 k Ω

, and

C = 11.5 pF

. Apart from

C_{C}

, which is implemented as a MIM capacitor, the other passive components are implemented outside the chip. The nominal frequency of oscillation is

f_{0} = 1.049 MHz

, while its maximum change is 6.6%. The power dissipation for the unloaded output is entered in the same Table and changes by a maximum of 17.5% compared to the circuit with typical parameters. Without the external resistor

R_{X}

, similar results are obtained, and the frequency change is slightly higher and amounts to 6.8%. After the Monte Carlo simulation on 500 samples, mean values of

f_{0} = 1.0493 MHz

and

P_{d i s s} = 210.2 μ W

and standard deviations of

σ_{f} = 4.512 kHz

and

σ_{P} = 1.504 μ W

were obtained.

Figure 17 shows the phase noise of the oscillator at 1.049 MHz, with three power supplies ±0.81 V, ±0.9 V, and ±0.99 V. At the offset frequency of 100 kHz, the phase noise is about

- 86 dBc / Hz

with a change of

0.55 dBc / Hz

. Under the same conditions, with a temperature change from −20 °C to 80 °C, the phase noise changes by approximately

0.5 dBc / Hz

. Table 6 shows the phase noise values for PVT variations, and the maximum change of phase noise is about

1 dBc / Hz

As Table 6 shows, the relative changes in frequency, power dissipation, and phase noise are relatively small and amount to

δ_{f} = 8.5 %

δ_{P} = 17.4 %

, and

δ_{P N} = 1.2 %

, respectively.

When the frequency of oscillation increases, so does the influence of parasitic Y and Z inductances and X capacitance. The selectivity of the positive feedback circuit is improved, and the rectangular pulses at the Z output change from square wave via trapezoidal wave to nearly sinusoidal. The maximum frequency for generating square-wave signals is around 10 MHz, and the power dissipation is 190 μW. The oscillator can regularly oscillate up to about 40 MHz in a nearly sinusoidal mode.

Table 7 gives comparative characteristics of individual square-wave generators. From many previously published works, designs by integrated oscillators and a similar achieved oscillation frequency were selected.

For comparison, the figure of merit (FOM) of the oscillator was used as the ratio of the maximum oscillation frequency to the power dissipation. The oscillator in [50] has a higher FOM than the proposed oscillator. Although it is simpler to implement and has fewer transistors, the square wave generator in [50] requires three resistors and one capacitor. The output has a high output impedance, so an additional buffer is required. In [51], the oscillator has a low output resistance, significantly higher power consumption, and a significantly lower FOM. The generator in [52] provides square wave outputs in the form of voltage and current that can also be used to output a differential square wave. It can electronically control the frequency, and due to the higher power consumption, this one also has a lower FOM than the proposed one. In [53], an oscillator with a CCCII is used. Although the circuit is simple, it has a relatively high power consumption and an output with high output resistance. Reference [54] shows a generator consisting of one MO-CFDITA and only one grounded capacitor, making the proposed generator circuit suitable for implementation in an integrated circuit. Although it has a high oscillation frequency, this generator provides an output square wave in the current mode. Of all the oscillators in Table 7, the circuit [55] has the highest FOM, but also has a current output and large die area, which is a consequence of implementing passive components in the chip. The circuits in [51,53] have a layout, but the area information is missing.

By comparing the proposed square wave oscillator with the results from previously published papers in Table 7, it can be concluded that this oscillator has a relatively high FOM, but also a great advantage in a small output impedance.

4. Conclusions

A CMOS rail-to-rail

V C I I^{-}

is designed with a power consumption of 157 μW, and a current and voltage buffer bandwidth of 298.3 MHz and 173.2 MHz, respectively. With a rail-to-rail 1 MHz sinusoidal excitation, total harmonic distortions in the voltage buffer are 0.29%. Distortions in the current buffer

V C I I^{-}

at a current amplitude of 200 μA are 1.19%, while in

V C I I^{+}

, similar distortions are obtained at 10-fold higher currents. The dynamic characteristics of

V C I I^{-}

were tested in a relaxation oscillator. Due to the wide bandwidth of the current and voltage buffer and a high slew rate, it was shown that a low-power relaxation oscillator with a frequency of up to 10 MHz and good stability can be made. The application of the realized rail-to-rail

V C I I

in our further research will focus on low-voltage, low-power energy harvesting applications. Future research will aim to improve the linearity of the low-power current buffer using feedforward and feedback techniques. Since the proposed VCIIs have good driving capabilities, they can drive switching transistors in high-frequency soft-switching DC-DC and switched capacitor converters [38,56].

Author Contributions

Conceptualization, R.D. and J.P.-B.; methodology, R.D. and J.P.-B.; validation, R.D.; formal analysis, R.D. and J.P.-B.; investigation, R.D. and J.P.-B.; resources, R.D. and J.P.-B.; data curation, R.D. and J.P.-B.; writing—original draft preparation, R.D. and J.P.-B.; writing—review and editing, R.D. and J.P.-B.; visualization, J.P.-B. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Data Availability Statement

The original contributions presented in the study are included in the article, further inquiries can be directed to the corresponding author.

Conflicts of Interest

The authors declare no conflicts of interest.

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Figure 1. Equivalent model of VCII.

Figure 2. Symbolic representation of the VCII.

Figure 3. The current buffer of the proposed

V C I I^{-}

Figure 3. The current buffer of the proposed

V C I I^{-}

Figure 4. Current-transfer function Y−X and its derivative.

Figure 5. Distortions of the CB at 1 MHz, as a function of the input current amplitude I_m.

Figure 6. The proposed rail-to-rail voltage buffer.

Figure 7. Voltage transfer function X−Z and its derivative.

Figure 8. The current buffer and the voltage buffer transfer function.

Figure 9. Schematic diagram of the current-driven NIC with

{VCII}^{-}

Figure 9. Schematic diagram of the current-driven NIC with

{VCII}^{-}

Figure 10. The proposed relaxation oscillator based on a

{VCII}^{-}

: (a) schematic diagram, (b) static characteristic of the oscillator’s active part.

Figure 10. The proposed relaxation oscillator based on a

{VCII}^{-}

: (a) schematic diagram, (b) static characteristic of the oscillator’s active part.

Figure 11. The small-signal oscillator circuit for equivalent resistance determination.

Figure 12. Typical voltage and current waveforms in the proposed oscillator at 1.045 MHz (

R_{F} = 22 k Ω

R_{X} \to \infty

C = 6.5 pF

Figure 12. Typical voltage and current waveforms in the proposed oscillator at 1.045 MHz (

R_{F} = 22 k Ω

R_{X} \to \infty

C = 6.5 pF

Figure 13. Static characteristics of the proposed oscillator with

R_{F 1} = 10 k Ω

and

R_{F 2} = 22 k Ω

, and with two external resistances

R_{X} = 100 k Ω

and

R_{X} \to \infty

Figure 13. Static characteristics of the proposed oscillator with

R_{F 1} = 10 k Ω

and

R_{F 2} = 22 k Ω

, and with two external resistances

R_{X} = 100 k Ω

and

R_{X} \to \infty

Figure 14. The frequency of oscillation vs.

C

and the relative error of the frequency estimation vs. frequency.

Figure 14. The frequency of oscillation vs.

C

and the relative error of the frequency estimation vs. frequency.

Figure 15. Frequency-dependent negative impedance

v = f (i)

: (a)

f = 1 MHz

, (b)

f = 5 MHz

, and (c)

f = 10 MHz

Figure 15. Frequency-dependent negative impedance

v = f (i)

: (a)

f = 1 MHz

, (b)

f = 5 MHz

, and (c)

f = 10 MHz

Figure 16. (a) Typical voltage and current waveforms in the proposed oscillator at 10 MHz, (b) The phase portrait at 10 MHz (

R_{F} = 22 k Ω

R_{X} = 100 k Ω

C = 0.79 pF

Figure 16. (a) Typical voltage and current waveforms in the proposed oscillator at 10 MHz, (b) The phase portrait at 10 MHz (

R_{F} = 22 k Ω

R_{X} = 100 k Ω

C = 0.79 pF

Figure 17. Phase noise in the 1.049 MHz relaxation oscillator for three supply voltages:

\pm 0.81 V

\pm 0.90 V

, and

\pm 0.99 V

(from bottom to top).

Figure 17. Phase noise in the 1.049 MHz relaxation oscillator for three supply voltages:

\pm 0.81 V

\pm 0.90 V

, and

\pm 0.99 V

(from bottom to top).

Table 1. Channel width and g_m/I_D parameters in the current buffer.

Transistor	W (μm)	g_m/I_D (S/A)
M₁, M₃, M₅	2.88	17.5
M₂, M₄, M₆	7.31	17.1
M₇, M₉	8.64	18.8
M₈, M₁₀	2.88	17
M₁₁, M₁₃	8.64	18.3
M₁₂, M₁₄	2.88	17.2

Table 2. Channel widths and g_m/I_D parameters in the voltage buffer.

Transistor	W (μm)	g_m/I_D (S/A)
M₁₅, M₁₆	10.8	18
M₁₇, M₁₈	2.88	15.2
M₁₉–M₂₂	8.64	14.7
M₂₃	1.44	14.8
M₂₄	3.24	13
M₂₅	4.32	9.1

Table 3. PVT Simulation results for

V C I I^{-}

Table 3. PVT Simulation results for

V C I I^{-}

Parameter	P				V(V_DD − V_SS)		T (°C)
Parameter	FF	FS	SF	SS	±0.99 V	±0.81 V	−20	25	80
r_Y [Ω]	107.6	113.4	108.2	112.3	101.8	123.3	110.1	110.3	116.4
L_Y [µH]	2.05	2.37	2.27	2.60	2.22	2.44	2.20	2.32	2.56
r_X [kΩ]	642.4	788.0	734.4	896.0	762.9	756.8	744.3	759.1	772.0
C_X [fF]	40.64	43.59	40.36	43.50	41.35	42.97	41.20	41.95	42.64
r_Z [Ω]	3.65	4.42	5.64	7.59	2.84	12.2	6.62	4.90	4.40
L_Z [µH]	1.16	1.60	1.89	2.89	1.09	3.52	2.26	1.74	1.54
β	1.151	1.118	1.121	1.091	1.145	1.091	1.110	1.119	1.128
α	0.9996	0.9995	0.9994	0.9992	0.9997	0.9998	0.9993	0.9995	0.9995
THD_Y-X [%]	1.32	1.21	1.20	1.09	1.19	1.23	1.09	1.19	1.30
THD_X-Z [%]	0.39	0.29	0.28	0.32	0.37	1.45	0.28	0.29	0.45
P_diss [µW]	186.9	159.6	153.5	137.6	218.5	118.8	141.5	155.9	174

* I_m = 100 µA.

Table 4. Monte Carlo simulation results for

V C I I^{-}

Table 4. Monte Carlo simulation results for

V C I I^{-}

MC	r_Y [Ω]	L_Y [µH]	r_X [kΩ]	C_x [fF]	r_Z [Ω]	L_Z [µH]	β	α	P_diss [µW]	THD_Y_-_X [%]	THD_X_-_Z [%]
Mean	111.2	2.091	752.1	41.47	5.014	1.751	1.120	0.9994	157	1.204	0.2866
Sigma	2.220	0.079	28.42	0.629	0.606	0.233	7.827 m	52.35 μ	6.99	28.07 m	10.837 m

Table 5. Comparison with other relevant previously reported class AB VCII topologies *.

	[38]	[35]	[36]	[37]	Proposed	Proposed
VCII type	positive	positive	positive	Positive	positive	negative
Class	AB	AB	AB	AB	AB	AB
α	0.94	0.972	1	0.953	0.9994	0.9994
α_BW [MHz]	191.5	50	100	50	173.2	173.2
β	1	0.996	0.987	0.993	1.044	1.119
β_BW [MHz]	86.6	165	169.7	11	311.1	298.3
r_Y [Ω]	602	23	1.88 k	973	97.48	110.4
r_X [Ω]	591 k	522 k	273.8 k	120 k	804.4 k	759.7 k
r_Z [Ω]	370	160	1.75 k	217	4.86	4.86
P_diss [µW]	70	120	179	393	136.6	157
THD_Y-X [%]	-	1.1	1	2.4	1	1.19
I_xpp @ 1 MHz	-	0.5 mA	1.22 mA	10 mA	2 mA	200 μA
THD_X-Z [%]	-	2.4	1	3.9	0.29	0.29
V_xpp @ 1 MHz	-	1.6 V	1.78 V	0.8 V	1.5 V	1.5 V
Number of transistors	19	37	12	38	31	35
Technology	0.18 μm	0.15 μm	0.18 μm	0.18 μm	0.18 μm	0.18 μm
Rail-to-rail	yes	yes	Yes	No	yes	yes

* The circuits in all reference works are powered by ±0.9 V.

Table 6. Oscillation frequency, power dissipation, and phase noise vs. PVT variation.

Parameter	P				V(V_DD − V_SS)		T (°C)
Parameter	FF	FS	SF	SS	±0.99 V	±0.81 V	−20	25	80
f₀ [MHz]	1.025	1.046	1.051	1.049	0.978	1.067	1.056	1.056	1.027
P_diss [μW]	216.8	210.4	209.8	205.7	229.3	192.6	207.8	209.9	213.1
PN [dBc/Hz]	−85.70	−86.41	−85.79	−86.76	−86.58	−86.03	−85.97	−86.05	−86.53

Table 7. Comparison of the proposed square-wave generator with previously reported generators.

Ref	[50]	[51]	[52]	[53]	[54]	[55]	Proposed
ABB	CCII	FTFN	ZC-CG-VDCC	CCCII	MO-CFDITA	CA	VCII
Num. of ABB	1	1	1	1	1	1	1
Passive elem.	3R, 1C	2R, 1C	2R, 1C	2R, 1C	1C	-	2R, 1C
Max Op. Freq.	50 MHz	5 MHz	4.385 MHz	4.99 MHz	50 MHz	7 MHz	10 MHz
Number of transistors	17	23	52	13	21	33	35
Area [μm²]	-	-	-	-	-	50,000	1250
Power supply	±0.75 V	±1.65 V	±1.0 V	±1.0 V	±1.25 V	±0.75 V	±0.9 V
Power dissip.	0.750 mW	2.81 mW	6.28 mW	0.6 mW	1.45 mW	11 μW	0.19 mW
FOM [kHz/μW]	66.7	1.78	0.70	8.32	34.5	636.36	52.6

FTFN, four-terminal floating nullor; ZC-CG-VDCC, Z-copy controlled gain voltage differencing current conveyor; CCCII, current controlled current conveyor; MO-CFDITA, multiple-output current follower differential input transconductance amplifier; CA, current amplifier.

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Djurić, R.; Popović-Božović, J. A CMOS Rail-to-Rail Class AB Second-Generation Voltage Conveyor and Its Application in a Relaxation Oscillator. Electronics 2024, 13, 3511. https://doi.org/10.3390/electronics13173511

AMA Style

Djurić R, Popović-Božović J. A CMOS Rail-to-Rail Class AB Second-Generation Voltage Conveyor and Its Application in a Relaxation Oscillator. Electronics. 2024; 13(17):3511. https://doi.org/10.3390/electronics13173511

Chicago/Turabian Style

Djurić, Radivoje, and Jelena Popović-Božović. 2024. "A CMOS Rail-to-Rail Class AB Second-Generation Voltage Conveyor and Its Application in a Relaxation Oscillator" Electronics 13, no. 17: 3511. https://doi.org/10.3390/electronics13173511

APA Style

Djurić, R., & Popović-Božović, J. (2024). A CMOS Rail-to-Rail Class AB Second-Generation Voltage Conveyor and Its Application in a Relaxation Oscillator. Electronics, 13(17), 3511. https://doi.org/10.3390/electronics13173511

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A CMOS Rail-to-Rail Class AB Second-Generation Voltage Conveyor and Its Application in a Relaxation Oscillator

Abstract

1. Introduction

2. Class AB Rail-to-Rail VCII

2.1. The Class AB Current Buffer

2.2. The Rail-to-Rail Voltage Buffer

2.3. Simulation Results for VCII

3. Proposed Relaxation Oscillator with VCII⁻

3.1. Circuit Description and Equivalent Model

3.2. Estimation of the Oscillation Period

3.3. Analysis and Design of the Proposed Relaxation Oscillator

3.4. Simulation Results for the Relaxation Oscillator

4. Conclusions

Author Contributions

Funding

Data Availability Statement

Conflicts of Interest

References

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A CMOS Rail-to-Rail Class AB Second-Generation Voltage Conveyor and Its Application in a Relaxation Oscillator

Abstract

1. Introduction

2. Class AB Rail-to-Rail VCII

2.1. The Class AB Current Buffer

2.2. The Rail-to-Rail Voltage Buffer

2.3. Simulation Results for VCII

3. Proposed Relaxation Oscillator with VCII−

3.1. Circuit Description and Equivalent Model

3.2. Estimation of the Oscillation Period

3.3. Analysis and Design of the Proposed Relaxation Oscillator

3.4. Simulation Results for the Relaxation Oscillator

4. Conclusions

Author Contributions

Funding

Data Availability Statement

Conflicts of Interest

References

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3. Proposed Relaxation Oscillator with VCII⁻