DAEM: A Data- and Application-Aware Error Analysis Methodology for Approximate Adders
<p>Structure of the equally segmented adder. All the sub-adders compute the result independently from one another. The carry does not propagate from one block to the other and, therefore, the latency of the design is significantly lower than that of its accurate counterpart.</p> "> Figure 2
<p>Structure of the speculative carry select adder. The output of each block is based on the carry from the previous block.</p> "> Figure 3
<p>Structure of the generic accuracy-configurable adder (GeAr). In this model, a specific low-latency approximate adder configuration can be defined by defining the number of resultant (<span class="html-italic">R</span>) bits and the number of propagation (<span class="html-italic">P</span>) bits. <span class="html-italic">R</span> defines the number of sum bits generated by each sub-adder, excluding the least significant sub-adder, as it generates <span class="html-italic">R</span> + <span class="html-italic">P</span> sum bits. <span class="html-italic">P</span>, in general, defines the number of bits in each sub-adder that are overlapping with its previous sub-adder. Thus, the GeAr configurations are represented in text using the ‘GeAr(<span class="html-italic">N</span>,<span class="html-italic">R</span>,<span class="html-italic">P</span>)’ notation.</p> "> Figure 4
<p>Structure of the error-tolerant adder type II (ETAII). The carry generation unit in each block computes the carry for its corresponding subsequent block.</p> "> Figure 5
<p>Design space of low-latency approximate adders: (<b>a</b>) for an 8-bit adder and (<b>b</b>) for a 10-bit adder.</p> "> Figure 6
<p>The structure of different GeAr adder configurations. (<b>a</b>) GeAr(8,2,2); (<b>b</b>) GeAr(9,2,3); (<b>c</b>) GeAr(10,2,2); (<b>d</b>) GeAr(11,2,3).</p> "> Figure 7
<p>(<b>a</b>) Comparison of the MSE evaluated using functional simulations and the MSE evaluated using the analytical model proposed by Mazahir et al. [<a href="#B23-information-14-00570" class="html-bibr">23</a>] (assuming uniform input distribution). (<b>b</b>) Execution time of functional simulations for template matching application as a function of number of input samples.</p> "> Figure 8
<p>(<b>a</b>). Example <math display="inline"><semantics> <msub> <mi>E</mi> <mrow> <mi>M</mi> <mi>A</mi> <mi>P</mi> </mrow> </msub> </semantics></math> for 8-bit ACA with <math display="inline"><semantics> <mrow> <mi>k</mi> <mo>=</mo> <mn>5</mn> </mrow> </semantics></math>, ESA with <math display="inline"><semantics> <mrow> <mi>k</mi> <mo>=</mo> <mn>2</mn> </mrow> </semantics></math> and SCSA with <math display="inline"><semantics> <mrow> <mi>k</mi> <mo>=</mo> <mn>2</mn> </mrow> </semantics></math>. The white-colored locations in <math display="inline"><semantics> <msub> <mi>E</mi> <mrow> <mi>M</mi> <mi>A</mi> <mi>P</mi> </mrow> </msub> </semantics></math> represent no error. (<b>b</b>) Joint input probability distribution generated using neighboring pixels of two visually different sets of grayscale images shown in (<b>c</b>).</p> "> Figure 9
<p>(<b>a</b>) Error generated and propagated by an <span class="html-italic">n</span>th adder. Figure is illustrated for <math display="inline"><semantics> <mrow> <mi>n</mi> <mo>=</mo> <mn>3</mn> </mrow> </semantics></math>, i.e., the 3rd adder, which is adding the sums obtained from the 1st and 2nd adders. (<b>b</b>) A configuration set <math display="inline"><semantics> <mrow> <mo>(</mo> <msub> <mi>c</mi> <mi>t</mi> </msub> <mo>)</mo> </mrow> </semantics></math> is defined by the type of approximate adder (adder variant) being used at each adder node. In the illustrated example of (<b>a</b>), each adder of the four-operand addition is using the same adder variant. Thus, the adder variant 1 is being used for each adder ((1), (2) and (3)). (<b>c</b>) Adjacency matrix provides the connectivity of the adder nodes.</p> "> Figure 10
<p>Proposed data- and application-aware error analysis methodology for approximate adders.</p> "> Figure 11
<p>The configurations of the GeAr adder model used for evaluation using synthetic data. (<b>a</b>) GeAr(8,1,4); (<b>b</b>) GeAr(8,1,5); (<b>c</b>) GeAr(8,2,2); (<b>d</b>) GeAr(9,2,3); (<b>e</b>) GeAr(10,2,4).</p> "> Figure 12
<p>Comparison of DAEM, state-of-the-art Mazahir et al. [<a href="#B23-information-14-00570" class="html-bibr">23</a>] and functional simulation results (<math display="inline"><semantics> <mrow> <mi>M</mi> <mi>E</mi> <mi>D</mi> </mrow> </semantics></math> and <math display="inline"><semantics> <mrow> <mi>M</mi> <mi>S</mi> <mi>E</mi> </mrow> </semantics></math>) obtained using 5 different configurations of GeAr for three different data distributions. Each GeAr configuration is represented in its generic form (<span class="html-italic">N</span>, <span class="html-italic">R</span>, <span class="html-italic">P</span>). The figure clearly shows that for uncorrelated data case, both the proposed and the state-of-the-art methods provide accurate estimates, and for the correlated case, the DAEM methodology provides better estimates than SOTA.</p> "> Figure 13
<p>Comparison of error in estimated MSE generated using DAEM, state-of-the-art by Mazahir et al. [<a href="#B23-information-14-00570" class="html-bibr">23</a>], and simulation results for two image processing applications for three datasets.</p> "> Figure 14
<p>Comparison of DAEM with state-of-the-art [<a href="#B23-information-14-00570" class="html-bibr">23</a>] and simulation results for audio low-pass filtering application. (<b>a</b>) Scenario 1 and (<b>b</b>) Scenario 2.</p> "> Figure 15
<p>Variations in per-frame MSE across frames of standard <math display="inline"><semantics> <mrow> <mi>c</mi> <mi>o</mi> <mi>n</mi> <mi>t</mi> <mi>a</mi> <mi>i</mi> <mi>n</mi> <mi>e</mi> <mi>r</mi> </mrow> </semantics></math> video for 4 × 4 approximate low-pass filtering application. The results are illustrated for 10 different configuration sets.</p> "> Figure 16
<p>Comparison of DAEM with state-of-the-art Mazahir et al. [<a href="#B23-information-14-00570" class="html-bibr">23</a>] and simulated results for a 4 × 4 low-pass filtering application for two standard videos: (<b>a</b>) container, (<b>b</b>) coastguard.</p> "> Figure 17
<p>Accurate-yet-efficient error estimations based on integration of multiple error estimation techniques that outperform others under certain specific conditions.</p> ">
Abstract
:1. Introduction
1.1. State-of-the-Art and Their Key Limitations
1.2. Our Novel Contributions
- DAEM employs two-dimensional joint input PMFs, populated over application data. These PMFs not only incorporate the specific input data distribution of the two operands, but they also characterize the joint probability of the occurrence of each possible input combination of the adder operands.
- Using a probabilistic analysis approach, DAEM provides a technique for the estimation of the PMF of the error at the output of an approximate adder. The PMF further allows the computation of the two predominantly used error matrices, i.e., mean square error (MSE) and mean error distance (MED). Furthermore, our DAEM methodology is extendable to datapaths composed of multiple adders.
- DAEM is applicable to a wide range of low-latency approximate adder designs, such as GDA, GeAr, ESA, ETAII, ETAIIM, ACA and ACAA [28]. We demonstrate this in Section 5 by using the proposed methodology for different GeAr configurations, as the GeAr adder model can be configured to mimic the functional characteristics (mainly the input–output transformation model) of most of these adder designs.
2. Background
3. Motivational Case Study for Analysis of the Impact of Application and Data on the Error Characteristics of Approximate Adders
- In real-world applications, such as a simple low-pass filtering application, the bits and operands to arithmetic components may be correlated. Thus, any assumption that violates this condition can result in significant deviation from the realistic/accurate results.
- Although functional simulations provide realistic estimates compared to the state-of-the-art error estimation techniques, their execution time is significantly longer than that for analytical methods. Thus, functional simulations cannot be used to explore a large design space in a reasonable amount of time.
4. DAEM: Data- and Application-Aware Error Analysis Methodology
4.1. Error Estimation for an Approximate Adder
Algorithm 1 Procedure for computation of for a single approximate adder |
Inputs: i.e., error map of a specific adder AND , i.e., the joint PMF of inputs of a specific adder |
Outputs: , i.e., PMF of error generated |
|
4.2. Error Estimation for an Intermediate Approximate Adder
- Error generated by Adder 3 itself, with a distribution characterized by . Note that can be computed by using the data- and application-aware joint input in Algorithm 1.
- Error propagated to Adder 3 that originates from the error in the input operands ( and ), with the distribution defined by . Note that is estimated by convolving the input error PMFs, assuming the inputs to be independent of each other, similar to the assumption considered in [39]. Thus,
4.3. Methodology
5. Results and Discussion
5.1. Comparison with State-of-the-Art [23]
- (1)
- Uniformly distributed uncorrelated inputs;
- (2)
- Uncorrelated Gaussian distribution with and ;
- (3)
- Correlated Gaussian distribution with and .
- Errors in the adders that are located in the earlier stages may trigger changes in the joint input PMFs of some/all the adders in the subsequent stages. However, as the variations in the joint input PMFs of low-latency adders are expected to be either small in magnitude or less frequent, and capturing these variations requires a significant amount of computation, to keep the model lightweight, these variations are ignored.
- The joint input PMFs of the adders for the testing set (i.e., the set used to perform functional simulations) can be different from the ones used for training (i.e., for data logging—Step-3 in Figure 10—in the DAEM methodology). These variations will further be discussed and analyzed in Section 5.2 and Section 5.3 for audio and video processing applications, respectively.
5.2. DAEM in Audio Processing
- Random Selection: The audio files were randomly divided into two groups. One of these groups was employed as training data for data logging (Step 3) in the DAEM methodology.
- Guided Selection: Each audio file was split into two parts. A new group of files was formed comprising the first half of these audio files, and it was used as the training data for data logging (Step 3) in the DAEM methodology.
5.3. DAEM in Video Processing
6. Evaluation of the Time Requirements for the Error Estimation Effort
- The first block is required to be executed only once and comprises Steps 1–5. It is assumed that s are pre-calculated, since they are only dependent on the adder variant/type. Accurate simulation comprising enumeration and data logging takes most of the time in this block.
- The second block (Steps 6–8) is executed T number of times to estimate the performance of each configuration set. However, these steps have a low computational cost.
7. Discussion of Limitations and Future Work
- Hardware accelerators are usually composed of cascaded stages where the inputs are fed to computing modules in the first stage and the output of the first stage is used as input to the second stage and so on. As the number of cascaded stages increases, the estimation of the joint input probability distribution of the computing modules becomes less accurate. This is because approximations in the earlier stages cause the joint input probability distribution of the modules in the latter stages to significantly deviate from the estimated joint input probability distribution. Hence, the proposed approach is highly effective for shallow accelerators, i.e., accelerators having a smaller number of cascaded stages, but may not produce reliable results for cases where the number of cascaded stages is large.
- The number of possible input combinations of a computing module increases exponentially with the increase in its input bit-width. This translates to huge memory requirements for the error maps and joint input probability distribution of the larger modules. For example, to store an error map of an 8-bit approximate adder in 8-bit integer format, a total of bytes (i.e., 64 KB) of memory is required; however, for a 16-bit adder, the memory requirement translates to bytes (i.e., 4 GB).
- One future direction can be building a holistic framework by integrating multiple different existing tools that offer a better accuracy–execution time trade-off in different scenarios and use a simple method/tool selection mechanism at the start to decide the most appropriate tool based on the input data characteristics and the given data path. For example, we can combine DAEM with simple convolution-based methods such as [23] and exhaustive simulations to build a framework that can offer an improved accuracy–execution time trade-off for a wide range of scenarios. However, such a framework requires thorough analysis to identify the strengths and weaknesses of different techniques, which can help in designing a low-cost selection mechanism. A high-level conceptual illustration of such a tool is presented in Figure 17.
- Another possible direction in addressing the limitations of the proposed approach is to explore machine learning to learn the dynamics of error propagation and masking in a data path and use the learned model to offer improved error estimation, especially for deeper data paths.
8. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
References
- Han, J.; Orshansky, M. Approximate computing: An emerging paradigm for energy-efficient design. In Proceedings of the 2013 18th IEEE European Test Symposium (ETS), Avignon, France, 27–30 May 2013; pp. 1–6. [Google Scholar]
- Venkataramani, S.; Chakradhar, S.T.; Roy, K.; Raghunathan, A. Approximate computing and the quest for computing efficiency. In Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, 8–12 June 2015; pp. 1–6. [Google Scholar]
- Mittal, S. A survey of techniques for approximate computing. ACM Comput. Surv. (CSUR) 2016, 48, 1–33. [Google Scholar] [CrossRef]
- Stanley-Marbell, P.; Alaghi, A.; Carbin, M.; Darulova, E.; Dolecek, L.; Gerstlauer, A.; Gillani, G.; Jevdjic, D.; Moreau, T.; Cacciotti, M.; et al. Exploiting errors for efficiency: A survey from circuits to applications. ACM Comput. Surv. (CSUR) 2020, 53, 1–39. [Google Scholar] [CrossRef]
- Xu, Q.; Mytkowicz, T.; Kim, N.S. Approximate computing: A survey. IEEE Des. Test 2015, 33, 8–22. [Google Scholar] [CrossRef]
- Mishra, A.K.; Barik, R.; Paul, S. iACT: A software-hardware framework for understanding the scope of approximate computing. In Proceedings of the Workshop on Approximate Computing across the System Stack (WACAS), Salt Lake City, UT, USA, 2 March 2014. [Google Scholar]
- Nair, R. Big data needs approximate computing: Technical perspective. Comm. ACM 2015, 58, 104. [Google Scholar] [CrossRef]
- Bornholt, J.; Mytkowicz, T.; McKinley, K.S. Uncertain <T>: Abstractions for uncertain hardware and software. IEEE Micro 2015, 35, 132–143. [Google Scholar]
- Bornholt, J.; Mytkowicz, T.; McKinley, K.S. Uncertain <T>: A first-order type for uncertain data. In Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems, Salt Lake City, UT, USA, 1–5 March 2014; Volume 49, pp. 51–66. [Google Scholar]
- Misailovic, S.; Carbin, M.; Achour, S.; Qi, Z.; Rinard, M.C. Chisel: Reliability-and accuracy-aware optimization of approximate computational kernels. ACM SIGPLAN Not. 2014, 49, 309–328. [Google Scholar] [CrossRef]
- Zhu, N.; Goh, W.L.; Zhang, W.; Yeo, K.S.; Kong, Z.H. Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2009, 18, 1225–1229. [Google Scholar]
- Taylor, M.B. Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse. In Proceedings of the DAC Design Automation Conference 2012, San Francisco, CA, USA, 3–7 June 2012; pp. 1131–1136. [Google Scholar]
- Wijtvliet, M.; Waeijen, L.; Corporaal, H. Coarse grained reconfigurable architectures in the past 25 years: Overview and classification. In Proceedings of the 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, 18–21 July 2016; pp. 235–244. [Google Scholar]
- Karunaratne, M.; Mohite, A.K.; Mitra, T.; Peh, L.S. Hycube: A cgra with reconfigurable single-cycle multi-hop interconnect. In Proceedings of the 54th Annual Design Automation Conference 2017, Austin, TX, USA, 18–22 June 2017; pp. 1–6. [Google Scholar]
- Peng, G.; Liu, L.; Zhou, S.; Yin, S.; Wei, S. A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection. IEEE J. Solid-State Circuits 2020, 55, 505–519. [Google Scholar] [CrossRef]
- Akbari, O.; Kamal, M.; Afzali-Kusha, A.; Pedram, M.; Shafique, M. Toward Approximate Computing for Coarse-Grained Reconfigurable Architectures. IEEE Micro 2018, 38, 63–72. [Google Scholar] [CrossRef]
- Ye, R.; Wang, T.; Yuan, F.; Kumar, R.; Xu, Q. On reconfiguration-oriented approximate adder design and its application. In Proceedings of the 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, 18–21 November 2013; pp. 48–54. [Google Scholar]
- Ebrahimi-Azandaryani, F.; Akbari, O.; Kamal, M.; Afzali-Kusha, A.; Pedram, M. Block-based carry speculative approximate adder for energy-efficient applications. IEEE Trans. Circuits Syst. II Express Briefs 2019, 67, 137–141. [Google Scholar] [CrossRef]
- Sengupta, D.; Sapatnekar, S.S. FEMTO: Fast error analysis in Multipliers through Topological Traversal. In Proceedings of the 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, USA, 2–6 November 2015; pp. 294–299. [Google Scholar]
- Ayub, M.K.; Hanif, M.A.; Hasan, O.; Shafique, M. PEAL: Probabilistic Error Analysis Methodology for Low-power Approximate Adders. ACM J. Emerg. Technol. Comput. Syst. (JETC) 2020, 17, 1–37. [Google Scholar] [CrossRef]
- Hanif, M.A.; Hafiz, R.; Hasan, O.; Shafique, M. PEMACx: A probabilistic error analysis methodology for adders with cascaded approximate units. In Proceedings of the 2020 57th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 20–24 July 2020; pp. 1–6. [Google Scholar]
- Liu, C.; Han, J.; Lombardi, F. An analytical framework for evaluating the error characteristics of approximate adders. IEEE Trans. Comput. 2015, 64, 1268–1281. [Google Scholar] [CrossRef]
- Mazahir, S.; Hasan, O.; Hafiz, R.; Shafique, M.; Henkel, J. Probabilistic error modeling for approximate adders. IEEE Trans. Comput. 2017, 66, 515–530. [Google Scholar] [CrossRef]
- Dou, Y.Q.; Wang, C.H. An Optimization Technique for PMF Estimation in Approximate Circuits. J. Comput. Sci. Technol. 2023, 38, 289–297. [Google Scholar] [CrossRef]
- Castro-Godínez, J.; Esser, S.; Shafique, M.; Pagani, S.; Henkel, J. Compiler-driven error analysis for designing approximate accelerators. In Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 19–23 March 2018; pp. 1027–1032. [Google Scholar]
- Sengupta, D.; Snigdha, F.S.; Hu, J.; Sapatnekar, S.S. An analytical approach for error PMF characterization in approximate circuits. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 2018, 38, 70–83. [Google Scholar] [CrossRef]
- Wu, Y.; Li, Y.; Ge, X.; Gao, Y.; Qian, W. An efficient method for calculating the error statistics of block-based approximate adders. IEEE Trans. Comput. 2018, 68, 21–38. [Google Scholar] [CrossRef]
- Jiang, H.; Han, J.; Lombardi, F. A comparative review and evaluation of approximate adders. In Proceedings of the 25th edition on Great Lakes Symposium on VLSI, Pittsburgh, PA, USA, 20–22 May 2015; pp. 343–348. [Google Scholar]
- Verma, A.K.; Brisk, P.; Ienne, P. Variable latency speculative addition: A new paradigm for arithmetic circuit design. In Proceedings of the Conference on Design, Automation and Test in Europe, Munich, Germany, 10–14 March 2008; pp. 1250–1255. [Google Scholar]
- Kahng, A.B.; Kang, S. Accuracy-configurable adder for approximate arithmetic designs. In Proceedings of the 49th Annual Design Automation Conference, San Francisco, CA, USA, 3–7 June 2012; pp. 820–825. [Google Scholar]
- Zhu, N.; Goh, W.L.; Yeo, K.S. An enhanced low-power high-speed adder for error-tolerant application. In Proceedings of the 2009 12th International Symposium on Integrated Circuits, ISIC’09, Singapore, 14–16 December 2009; pp. 69–72. [Google Scholar]
- Shafique, M.; Ahmad, W.; Hafiz, R.; Henkel, J. A low latency generic accuracy configurable adder. In Proceedings of the 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC 2015), San Francisco, CA, USA, 8–12 June 2015; pp. 1–6. [Google Scholar]
- Miao, J.; He, K.; Gerstlauer, A.; Orshansky, M. Modeling and synthesis of quality-energy optimal approximate adders. In Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, 5–8 November 2012; pp. 728–735. [Google Scholar]
- Stefanidis, A.; Zoumpoulidou, I.; Filippas, D.; Dimitrakopoulos, G.; Sirakoulis, G.C. Synthesis of Approximate Parallel-Prefix Adders. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2023. [Google Scholar] [CrossRef]
- Zhu, N.; Goh, W.L.; Yeo, K.S. Ultra low-power high-speed flexible probabilistic adder for error-tolerant applications. In Proceedings of the 2011 International SoC Design Conference, Jeju, Republic of Korea, 17–18 November 2011; pp. 393–396. [Google Scholar]
- Zhu, N.; Goh, W.L.; Wang, G.; Yeo, K.S. Enhanced low-power high-speed adder for error-tolerant application. In Proceedings of the 2010 International SoC Design Conference, Incheon, Republic of Korea, 22–23 November 2010; pp. 323–327. [Google Scholar]
- Mohapatra, D.; Chippa, V.K.; Raghunathan, A.; Roy, K. Design of voltage-scalable meta-functions for approximate computing. In Proceedings of the 2011 Design, Automation & Test in Europe, Grenoble, France, 14–18 March 2011; pp. 1–6. [Google Scholar]
- Du, K.; Varman, P.; Mohanram, K. High performance reliable variable latency carry select addition. In Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 12–16 March 2012; pp. 1257–1262. [Google Scholar]
- Leon-Garcia, A.; Leon-Garcia, A. Probability, Statistics, and Random Processes for Electrical Engineering, 3rd ed.; Pearson/Prentice Hall: Upper Saddle River, NJ, USA, 2008. [Google Scholar]
- Liang, J.; Han, J.; Lombardi, F. New metrics for the reliability of approximate and probabilistic adders. IEEE Trans. Comput. 2012, 62, 1760–1771. [Google Scholar] [CrossRef]
- Stork, J.A.; Spinello, L.; Silva, J.; Arras, K.O. Audio-based human activity recognition using non-Markovian ensemble voting. In Proceedings of the RO-MAN 2012, Paris, France, 9–13 September 2012; pp. 509–514. [Google Scholar]
T | Mazahir [23] | Simulations | DAEM |
---|---|---|---|
10 | 0.005 | 18,416.00 | 71.687 + 0.006 |
30 | 0.015 | 55,245.00 | 71.687 + 0.018 |
60 | 0.031 | 110,497.00 | 71.687 + 0.036 |
90 | 0.047 | 165,746.00 | 71.687 + 0.054 |
120 | 0.062 | 220,995.00 | 71.687 + 0.073 |
Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content. |
© 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).
Share and Cite
Hanif, M.A.; Hafiz, R.; Shafique, M. DAEM: A Data- and Application-Aware Error Analysis Methodology for Approximate Adders. Information 2023, 14, 570. https://doi.org/10.3390/info14100570
Hanif MA, Hafiz R, Shafique M. DAEM: A Data- and Application-Aware Error Analysis Methodology for Approximate Adders. Information. 2023; 14(10):570. https://doi.org/10.3390/info14100570
Chicago/Turabian StyleHanif, Muhammad Abdullah, Rehan Hafiz, and Muhammad Shafique. 2023. "DAEM: A Data- and Application-Aware Error Analysis Methodology for Approximate Adders" Information 14, no. 10: 570. https://doi.org/10.3390/info14100570
APA StyleHanif, M. A., Hafiz, R., & Shafique, M. (2023). DAEM: A Data- and Application-Aware Error Analysis Methodology for Approximate Adders. Information, 14(10), 570. https://doi.org/10.3390/info14100570