A Novel Offset Cancellation Based on Parasitic-Insensitive Switched-Capacitor Sensing Circuit for the Out-of-Plane Single-Gimbaled Decoupled CMOS-MEMS Gyroscope

1. Introduction

Generally speaking, MEMS gyroscopes only have relatively small detection capacitances; therefore, the sensing circuit design is very important. The sensing mechanisms of MEMS gyroscopes are mainly categorized into piezoresistive [1–5] and capacitive [6–13] mechanisms. Capacitive gyroscopes have simpler structure and hence lower fabrication cost. In addition, they provide lower power consumption, higher sensitivity, and higher reliability as well as lower nonlinearity, lower temperature dependency, lower noise, and lower drift. Capacitance is also easily available in silicon technology because it does not require special materials and process steps. On the other hand, the piezoresistive sensing scheme is widely used in accelerometers. If the gyroscopes use piezoresistive materials, they should be driven in their primary modes with different mechanism because piezoresistive materials cannot induce passive nature by themselves [14]. In addition, its sensitivity is low, and its temperature dependency is high compared to the capacitive gyroscope. Hence, it is mainly used in low-end products.

Capacitive sensing circuits are categorized into synchronous [15], switched-capacitor [12,16–18], and fully differential circuits [8,11,19,20]. The transfer functions of the first two are independent of parasitic capacitance, and they can cancel the flicker noise and DC offset voltage to provide high accuracy. The synchronous sensing circuit requires bias control with either a large value off-chip or large-area integrated resistive circuit component [15]. In addition, in the frequency response, the transfer function of the synchronous sensing circuit has a zero point that increases the phase delay so that it cannot control feedback. The architecture of the fully differential sensing circuit is simple and contains no charge cancellation error, but its signals are attenuated by parasitic capacitance [19]. The switched-capacitor circuit technique is based on the realization that the capacitor and switch are equivalent to a resistor for reducing the layout area [16–18]. This technique can realize a variety of other signal-processing blocks, such as gain-stage, voltage-controlled oscillators (VCOs), and modulators. The switched-capacitor circuit can provide stability but it reduces the open-loop gain. In addition, the switched-capacitor circuit provides a virtual ground and robust DC biasing at the sensing node so that the sensed signal is insensitive to parasitic capacitance and undesirable charging. This circuit also offers a wide range of techniques to suppress offset and low-frequency noise, such as correlated double sampling (CDS) and programmable capacitor array (PCA). Thus, this circuit is very suitable for gyroscope measurement. A novel parasitic-insensitive switched-capacitor (PISC) sensing circuit is designed in order to get high sensitivity and ultra linearity and reduce the parasitic effect for the out-of-plane single-gimbaled decoupled gyroscope (SGDG) in this study.

This paper is organized as follows: in Section 2, the PISC circuit design is briefly introduced. The simulation results are presented in Section 3. The experimental results are presented in Section 4. Finally, the conclusions are given in Section 5.

2. Circuit Design

The on-chip sensing circuit uses the switched-capacitor sensing circuit that detects the capacitance change due to the deflection of the proof mass. During the sampling phase of a traditional switched-capacitor amplifier, it only samples the input, sets the output to zero, and provides no amplification. This raises concern about its stability, and reduces the open-loop gain. The capacitors used are known as double-poly capacitors. There also exists a substantial parasitic capacitance. In order to reduce the parasitic effect, we propose the PISC sensing circuit, as shown in Figure 1 [16,17]. Here, the “RESET” switches are only utilized for discharging the capacitors initially. The C_Gyro is capacitance of detection of the gyroscope, the C_Ref is initial capacitance of detection of the gyroscope and the C_Elec is amplification capacitance. V_CM is common mode voltage, and its value is V_DD/2. In this study, the V_CM is set to 1.65 V.

At the beginning, the input signals voltages of the circuit are +1.65 V and −1.65 V. In order to maintain the cut-off condition for all the substrate-to-channel junctions, the substrate is usually connected to the most negative power supply in an NMOS circuit (the most positive in a PMOS circuit) [18]. Thus, we use the concept of voltage translation to change the input signal voltage. The input signal V_i1(t) changes to V_DD, and the other V_i2(t) changes to zero.

As shown in Figure 2(a), in the sampling mode, Φ₂ is on and Φ₁ is off, allowing the voltage across C_Gyro and C_Ref to track V_i1(t) and V_i2(t) while the operational amplifier (OP-amp) and C_Elec hold the previous value. In the transition to the amplification mode, the charge stored on C_Gyro and C_Ref are transferred to C_Elec through the virtual ground node, as shown in Figure 2(b).

The results in the transfer function for this switched-capacitor circuit are given by:

Note that Equation (1) represents its gain coefficient as the ratio of the difference capacitance and C_Elec. The z^−1/2 represents a period delay and can be ignored [16]. The behavior of the circuit with respect to parasitic capacitances is plotted in Figure 3 [16].

Here, C_p1 is continuously being charged to V_i1(t) and discharged to the common mode (V_CM). However, when Φ₂ is turned on, the fact that C_p1 is also charged to V_i1(t − 1) does not affect the charge that is placed on C_Gyro. When Φ₁ is turned on, C_p1 is discharged through the Φ₁ switch attached to its node, and none of the discharging current passes through C_Gyro to affect the charge accumulating on C_Elec. Therefore, it does not affect the circuit operation. In addition, C_p2 is either connected to V_CM through the Φ₂ switch or to the virtual ground through the Φ₁ switch. Since C_p2 always remains discharged, it does not affect the operation of the circuit. Similarly, the operations of C_p3 and C_p4 do not effect as C_p1 and C_p2. The effect of C_p5 on the transfer function is small since it is always connected to the virtual ground of the OP-amp. Finally, C_p6 is connected to the OP-amp output. Although it may affect the speed of the OP-amp, it would not affect the final settling point of the OP-amp output.

A switched-capacitor circuit is realized with basic building blocks such as the OP-amp, capacitors, switches, and non-overlapping clocks. The OP-amp circuit is shown in Figure 4. To improve the circuit stability, the OP-amp must provide a high enough stability margin. The folded-cascode OP-amp architecture is selected to provide the phase margin of 78.906°. The input differential pairs use large devices with a parallel symmetric layout for good matching, thereby reducing the input voltage offset and flicker (1/f) noise. To increase the phase margin of OP-amp, a large output compensation capacitor of up to 3.8 pF is used; it is made of double poly (poly1 and poly2). Table 1 provides a list of the device sizes.

The requirements for switches used in this paper are that they have very high off resistance and low on resistance, and introduce no offset voltage when turned on. In order to achieve the full signal range of 0 to 3.3 V, we used a negative triggered CMOS transmission gate, as shown in Figure 5 [16]. To guarantee that the charge is not inadvertently lost, we adopt the non-overlapping clock, as shown in Figure 6, which is used to eliminate the clock feed-through influence [16,17]. It has two logic signals running at the same frequency and is changed in such a way that at no time are both signals high.

A sensing circuit usually requires an ADC. In general, the output voltage for the sensing circuit is weak and small. A high resolution ADC is necessary for acquiring such a feeble signal. The ΣΔ ADC is the best choice for this application. It uses the over-sampling principle, noise shaping and decimation filtering to achieve the high resolution. It consists of a ΣΔ modulator and a decimation filter. In addition, the ΣΔ ADC operates in the discrete-time domain and is implemented using the switch-capacitor circuit technique. The switch-capacitor circuit can only be realized in MOS devices, not in bipolar transistors. In other words, the sensing circuit fabricated in the digital CMOS process is suitable for generating the digital output using ΣΔ ADCs. The behavior simulation model shown in Figure 7 is adopted for the ΣΔ modulator design to avoid the integrator overload and to satisfy the system requirements. The design is the second order ΣΔ modulator with a one-bit quantizer. The decimation digital filter is implemented by down-sampling and a comb filter. The discrete-time integrator parameters of K1 and K2 for the ΣΔ modulator are 0.1 and 0.5, respectively.

The circuit design for the ΣΔ modulator is shown in Figure 8. Here, “OTA1” and “OTA2” are folded-cascode OP-amps, as shown in Figure 4. The “COMP” indicates the comparator circuit, as shown in Figure 9. The “RESET” switches are only utilized for discharging the capacitors initially. The circuit is implemented using the switch-capacitor technique and controlled by a non-overlap clock circuit, as shown in Figure 6, which is used to eliminate the clock feed-through influence.

3. Simulation Results

In this paper, the simulation results for circuit design are the post-layout simulation results.

4. Experimental Results

The proposed PISC circuit combined one-bit SDM circuit has been tested. The chip, shown in Figure 22, is 2.817 mm × 1.513 mm, and contains three PISCs, three CLKs, and three SDM blocks.

Here, the PISC1 means the PISC circuit has the C_Gyro = 500 fF, the PISC2 means the PISC circuit has the C_Gyro = 540 fF, and the PISC3 means the PISC circuit has the C_Gyro = 460 fF. CLK indicates the non-overlapping clock circuit. A photograph of the test PCB block is shown in Figure 23. The measured voltage result for the PISC2 circuit (C_Gyro = 540 fF) is 2.72 V, as shown in Figure 24. The pre- and post-layout simulation results are shown in the up-right corner in Figure 24. These results are very similar. Other results are summarized in Table 6. The experimental results of the PISC circuit using signal processing have significantly smaller voltage offset and noise floor than those without using signal processing, as shown in Figure 25.

Table 7 summarizes a comparison on the results of the proposed PISC circuit and other capacitive sensing circuits reported in the literature. It can be noted that the proposed PISC circuit has the smallest noise floor and chip area. The voltage offset is comparable to [11] but smaller than the remaining solutions listed in Table 7. The capacitive sensing circuits in [11] is simulation result. The resolution is comparable to [12] but smaller than other capacitive sensing circuits already presented in the literature. For standalone applications, the device gives an analog output and provides digital output with embedded one-bit ΣΔ ADC.

5. Conclusions

In this study, we present a novel PISC sensing circuit design in order to obtain high sensitivity and ultra linearity for an out-of-plane gyroscope. From the simulation results, we can see that the proposed PISC circuit has a good sensitivity of 9.16 mV/°/s and a high linearity of 99.16% in a wide dynamic range from −300 °/s to 300 °/s. The experimental results also show a good performance. In addition, the PISC circuit can use signal processing to cancel the offset and noise. Thus, this circuit is very suitable for gyroscope measurement.