Reliability issues, such as soft errors, process variations and Negative Bias Temperature Instability (NBTI), become dominant on Field Programmable Gate Arrays (FPGAs) fabricated in a nanometer process. We focus on aging degradation by NBTI, which causes threshold voltage shifts on PMOS transistors. We characterize delay degradation in the routing structures on FPGAs. The rising and falling delays vary due to NBTI and heavily depend on circuit configurations. In the independent routing switch, the delay fluctuation due to NBTI can be minimized by transistor sizing. The falling delay does not change after 10-years degradation. In the routing structures composed of the routing switches and wires, the delay fluctuation depends on the wire length and can be minimized to optimize the wire length. We also show that the signal flipping can reduce the delay degradation from 11.3% to 2.76% on the routing resources.