IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 3, MARCH 2008 1047 Switching Characterization of Cascaded Multilevel-Inverter-Controlled Systems Rajesh Gupta, Student Member, IEEE, Arindam Ghosh, Fellow, IEEE, and Avinash Joshi Abstract—In this paper, the method of triangular carrier switching control of two-level inverters is extended to cascaded multilevel inverters using phase-shifted multicarrier unipolar pulsewidth modulation (PWM). The condition for smooth modulation is obtained using the Bessel’s function representation of the PWM output and the switching condition of the multilevelinverter-controlled system. A method is proposed for the determination of the minimum amplitude of the triangular carrier for smooth modulation at fixed switching frequency. It is shown that the multilevel modulation based on the phase-shifted carriers significantly reduces the ripple magnitude in the switching function and allows the use of a smaller carrier amplitude under closed loop. This increases the forward gain and, hence, improves the tracking characteristics. The proposed cascaded multilevel inverter control is implemented for the operation of a distribution static compensator (DSTATCOM) in the voltage control mode. The experimental verification of the theoretical and simulation results is provided through a field-programmable gate array (FPGA) based control of a laboratory model of a single-phase DSTATCOM. Index Terms—Bessel’s function, carrier amplitude, cascaded multilevel inverter, distribution static compensator (DSTATCOM), field-programmable gate array (FPGA), multilevel modulation, switching control. I. I NTRODUCTION HE BASIC motivation for the use of multilevel inverters is the reduction of voltage stress on the switching devices [1]. A cascaded multilevel inverter is a cost-effective option due to the series connections of identical H-bridge modules. The use of phase-shifted multicarrier unipolar pulsewidth modulation (PWM) reduces the harmonic contents of the voltage delivered by the cascaded multilevel inverter [2], operating at a lower switching frequency because of low switching loss. Applications such as medium-voltage distribution system compensation use cascaded multilevel inverters as the voltage source inverters (VSIs) for compensating devices [3], [4]. The hysteresis-based instantaneous method of control has been a preferred method for accurate and fast dynamic performance of two-level inverter-controlled systems [5]–[8]. Recently, a hysteresis-based control has been used for the cascaded multilevel topology [4]. However, the method suf- T Manuscript received May 1, 2006; revised September 7, 2007. R. Gupta is with the Department of Electrical Engineering, M. N. National Institute of Technology, Allahabad 211 004, India (e-mail: rajeshgupta310@ rediffmail.com). A. Ghosh is with School of Engineering Systems, Queensland University of Technology, Brisbane, Qld. 4001, Australia (e-mail: a.ghosh@qut.edu.au). A. Joshi is with the Department of Electrical Engineering, Indian Institute of Technology, Kanpur 208 016, India (e-mail: ajoshi@iitk.ac.in). Digital Object Identifier 10.1109/TIE.2007.896274 fers from the disadvantages of variable switching frequency and unequal switching stress among various switches. The satisfactory performance is obtained on an average basis only after a sequential change in the switching order. The method of triangular carrier switching control is well known for the closed-loop control of two-level inverters [5]–[9]. The method yields dynamic performance close to the hysteresis control and, additionally, provides a constant switching frequency. The important limitation of this method is that it leads to a tracking error in the steady state for low-frequency references that is proportional to the carrier amplitude [6], whereas the value of the carrier amplitude cannot be arbitrarily reduced and is limited by the ripple magnitude of the switching function. The carrier amplitude forms an important design parameter and is difficult to a priori estimate for smooth modulation at the fixed switching frequency. There has been a recent trend for the generalization of the two-level inverter control techniques to the multilevel inverters [10]–[12]. In this paper, the method of triangular carrier switching control of two-level inverters is extended for the cascaded multilevel-inverter-controlled systems. A multilevel output voltage is generated following the phase-shifted multicarrier unipolar PWM for the cascaded inverters. The method leads to a fixed switching frequency operation with uniform distribution of the switching stress among all the switches. The condition for smooth modulation is obtained using the Bessel’s function representation of the PWM output [2] and the switching condition of multilevel inverters. A method is proposed for the determination of the minimum amplitude of a triangular carrier for the smooth modulation at a fixed switching frequency of the multilevel control. The proposed cascaded multilevel control is implemented for the operation of a distribution static compensator (DSTATCOM) in the voltage control mode [6] and verified through an experimental model of a low-voltage distribution system. II. DSTATCOM IN V OLTAGE C ONTROL M ODE A single-phase structure of the DSTATCOM compensated distribution system is shown in Fig. 1. A DSTATCOM is a VSIbased device. When operated in a voltage control mode, the DSTATCOM can control the voltage vt at the point of common coupling (PCC) [6], [13]. In the present application, the VSI is realized using a cascaded multilevel inverter. The load is supplied from voltage source vs through a feeder (Rs , Ls ). It is assumed that the load is a nonlinear rectifier type with input impedance (Ll , Rl ). For this load, resistance Rdc in parallel with capacitor Cdc is connected across the full bridge rectifier. 0278-0046/$25.00 © 2008 IEEE 1048 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 3, MARCH 2008 III. M ODULATION P RINCIPLE FOR C ASCADED M ULTILEVEL I NVERTERS Fig. 1. Single-phase model of DSTATCOM compensated distribution system. In [14], it is shown that such loads can be represented by a periodic voltage source vd . The shunt impedance is denoted by (LT , RT ). The filter capacitor Cf is connected across the PCC. The currents flowing through the different branches are source current is , load current il , filter capacitor current icf , and injected shunt current ish . The net voltage at the output of the VSI is uo Vdc , where uo and Vdc are the control signal and the total dc link voltage of the VSI, respectively. Choosing the state vector xT = [ ish icf vt il ] and output as the PCC voltage vt , the following state space representation is obtained: ẋ = Ax + b1 vs + b2 uo + b3 vd , vt = cx = [ 0 0 1 0 ]x (1) where the matrices A, b1 , b2 , and b3 are given in Appendix I. The sliding mode control is used here to control the voltage at the PCC [6], [15]. The switching function for the sliding mode control is defined as se = k1 (v̇tref − v̇t ) + k2 (vtref − vt ) = k1 ė + k2 e (2) where k1 and k2 are positive gains, vtref is the reference for PCC voltage, and e is the voltage tracking error. It is shown in [6] and [15] that under the ideal sliding mode implementation (i.e., uo = +1 for se > 0 and uo = −1 for se < 0), the switching surface defined by (2) is stable as long as the eigenvalue λ = −(k2 /k1 ) lies in the left half of the s plane. The switching function (2) will converge to the origin depending on the time constant T = k1 /k2 , and vt will follow vtref in the steady state. Note that the control law (2) requires the derivative of the terminal voltage, i.e., v̇t . This can be easily obtained from the measurement of the filter capacitor current icf and dividing it by the capacitance Cf . Therefore, the switching function (2) can be considered as the output of an ideal proportional plus derivative controller without any need of the external differentiator. The ideal sliding mode requires infinite frequency for switching elements leading to asymptotic convergence. However, the practical switching devices, e.g., insulated gate bipolar transistors (IGBTs), have finite switching frequency. To bring the switching frequency into the limits of practical devices, there are various nonideal sliding mode control strategies [6], [9]. These lead to stable convergence with the evolution of states around the switching surface. Multilevel modulation of a VSI under closed loop is yet another nonideal control strategy; a generalized methodology of which is now developed. Fig. 2 shows the triangular carrier switching control strategy extended for cascaded multilevel inverters. The control variable sx is compared with the reference sr , where the control variable and reference may represent voltage, current, or, in case of state feedback, their combinations. For DSTATCOM control presented in the previous section, these represent voltage. The error e is then passed through the controller to obtain the switching function se . This is then compared with the triangular carriers for multilevel modulation. A suitably small hysteresis band h is used to avoid any multiple crossing under closed loop [6]. For an n-level topology shown in Fig. 2, where n = 3, 5, 7, . . . , the total number of H-bridges required is N = (n − 1)/2. Each of the switches Sw11 to SwN 4 consists of a power semiconductor device (e.g., IGBT) and an antiparallel diode. The total dc link voltage Vdc is divided among these N H-bridges such that each H-bridge is applied with a dc link voltage of Vdc /N . For H-bridge 1, the switching function se is compared with the carrier vtri1 of frequency ωc , amplitude Vtri , and zero phase. Assume the switching function se to be a sinusoidal modulating signal, i.e., Mi Vtri cos(ωo t), where ωo is the frequency of modulating signal, and Mi is the modulation index that lies between 0 and 1 for linear range [16]. Later in Section IV, the effect of switching ripples present in the switching function is analyzed. Following the principle of unipolar PWM [16], the switching function se is modulated with the carrier vtri1 for the first leg as follows: se − vtri1 > +h, then Sw11 is on, leading to uA1 = +1 (3.1a) and vA1O1 = +Vdc /(2N ) se − vtri1 < −h, then Sw14 is on, leading to uA1 = −1 (3.1b) and vA1O1 = −Vdc /(2N ) where O1 is the hypothetical midpoint of the dc source Vdc /N . Similarly, for the second leg −se − vtri1 > +h, then Sw13 is on, leading to uB1 = +1 and vB1O1 = +Vdc /(2N ) (3.2a) −se − vtri1 < −h, then Sw12 is on, leading to uB1 = −1 and vB1O1 = −Vdc /(2N ). (3.2b) Note that the switches of the same leg are complementary. Therefore, the net voltage levels obtained for H-bridge 1 between points A1 and B1 are +Vdc /N , 0, and −Vdc /N . This yields three-level output voltage vA1B1 . Similarly, for other H-bridges, the process given in (3) is repeated with the carrier vtril (l = 2, 3, . . . , N ), having the same amplitude Vtri and frequency ωc , but shifted in phase by angle (l − 1)π/N , where l represents the lth H-bridge [17]. This leads to the individual three-level output for each H-bridge. These voltages, when added, as shown in Fig. 2, yield an n-level output voltage vA1BN . As an example for a five-level inverter (n = 5), two H-bridges (N = 2) are used, and the total dc link voltage Vdc is equally divided between the two H-bridges, i.e., Vdc /2. GUPTA et al.: SWITCHING CHARACTERIZATION OF CASCADED MULTILEVEL-INVERTER-CONTROLLED SYSTEMS Fig. 2. 1049 Multicarrier PWM of a cascaded multilevel inverter. The phase shifts of the carriers are 0 and π/2 rad. This gives three-level output voltages vA1B1 and vA2B2 across each H-bridge. The two voltages, when added, yield five-level output voltage vA1B2 . The expression for the PWM output uo of the n-level inverter using normalization with respect to the dc link voltage Vdc , i.e., vA1BN /Vdc , is written as [2], [17] uo (t) = Mi cos(ω0 t) + ∞ ∞ 4

1 J2k−1 (N mπMi ) π m=1 2N m k=−∞ × cos [(N m + k − 1)π] cos [2N mωc t + (2k − 1)ωo t] (4) where Jq (x) represents the Bessel’s function of the first kind of order q and argument x. For an n-level inverter, the voltage stress of the semiconductor switches is 1/N times the total dc link voltage Vdc . Using the phase-shifted unipolar PWM, the harmonic spectrum of the inverter output voltage contains switching components at 2N times the frequency of the carrier ωc , its integral multiples [index m in (4)], and the side bands shifted from these in the multiples of the fundamental frequency ωo [index k in (4)]. The magnitude of switching harmonics in the PWM output is also proportionally reduced by a factor 1/2N . These two conditions considerably reduce the ripples in the switching function se , and this allows the smooth modulation of the switching function for multilevel inverters with a carrier signal of small amplitude. IV. S TEADY -S TATE S WITCHING Recently, the analysis of fixed switching frequency control of two-level inverters has been done using the concept of Fig. 3. Block diagram of the multicarrier PWM switching controlled system. forced switching [6]. The method is based on the assumption that the switching function se (t) consists only of switching ripples that are obtained by considering PWM as square-shaped pulse input at the frequency of carrier ωc . However, the effect of the low-frequency modulating signal is neglected. In this section, the analysis of the triangular carrier switching control of cascaded multilevel inverters is done considering that the switching function se (t) consists of switching ripples that are obtained using the second term of (4), which is a pulsed input of varying width carrying frequency component at 2N times the frequency of the carrier ωc , its integral multiples, and side bands, as discussed earlier. Additionally, the switching function se (t) also contains a low-frequency modulating signal given by Mi Vtri cos(ωo t). The block diagram of a multicarrier PWM switching controlled system is shown in Fig. 3. Block M in Fig. 3 represents the normalized modulation of the multilevel inverter of Fig. 2. The normalized PWM output voltage uo given by (4) drives the linear system G. This linear system G is assumed to be stable, i.e., all its poles lie in the left half of the s plane. Also, the number of poles is greater than the number of zeros to have low-pass filtering characteristics. The control variable sx of the linear system is fed back for the comparison with the reference variable sr . The low-frequency error e generated out of the comparison of the two variables is 1050 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 3, MARCH 2008 the switching function that carries a low-frequency modulating signal and high-frequency switching components. The figure shows the carrier phase-shifted unipolar PWM with five-level output uo . The carrier frequency is 1.0 kHz, and, therefore, the harmonic cancellation up to 4.0 kHz is achieved. Note, however, that all the switches of two H-bridges uniformly operate at 1.0 kHz. A. Smooth Modulation Condition In steady state, the low-frequency component of uo , given by (4), is used to compensate the tracking error of the system. Therefore, the reference sr in Fig. 3 is assumed to be zero for the analysis of the switching components in the steady state. The only leftover component of low frequency after propagation from uo to se is the modulating signal. The amplitude of this modulating signal depends on the amplitude of the triangular carrier Vtri and the modulation index Mi . Assuming a modulating signal of fundamental frequency ωo , its expression is written as [17] mse (t) = Mi Vtri cos(ωo t). Fig. 4. (a) Generation of switching function. (b) Carrier phase-shifted unipolar PWM of switching function for five-level inverters. then passed through the controller Gc to generate the switching function se , as shown in Fig. 4(a). The low-frequency component of uo , i.e., the first term of (4), is the desired control signal for tracking the reference. The high-frequency component, i.e., the second term, corresponds to the switching phenomenon in the inverter and propagates into the system after filtering through the linear components. Under the triangular carrier switching control scheme, the switching function carries the switching components in addition to the low-frequency modulating signal, as shown in Fig. 4(a). For smooth modulation, the slope of the switching function should never exceed the slope of the triangular carrier to make a clean intersection [8]. This leads to a fixed switching frequency (i.e., at the frequency of carrier ωc ) operation of the switches of the inverter under closed loop. There is a minimum amplitude of the carrier above in which the slope of the carrier is always larger than the slope of the switching function at every intersection over one cycle of the fundamental frequency ωo such that the modulation is always at the frequency of the carrier [6]. This has been called smooth modulation for multilevel inverters in the following sections. Below this minimum amplitude, the inverter enters into the high-frequency chaotic switching operation. Fig. 4(b) shows the smooth modulation of (5) The value of the modulation index Mi for fixed system parameters under closed loop depends on the reference sr , source voltage vs , and loading condition. The propagation of switching component from uo to se in steady state follows the principle of linear theory [18], i.e., for input A cos(ωt), where A is the amplitude, and ω is the frequency of the input sinusoid, the output of the linear system with a transfer function Gt (s) in the steady state is A|Gt (jω)| cos(ωt + θ), where θ = tan−1 [imag(Gt (jω))/ real(Gt (jω))]. The transfer function Gt (s) is defined as Gt (s) = −G(s)Gc (s) for the system shown in Fig. 3. Using the principle of superposition, the switching component of se is obtained using the second term of (4) as sse (t) = ∞ ∞ 1 4

J2k−1 (N mπMi ) π m=1 2N m k=−∞ × cos {(N m+k−1)π}|Gt j {2N mωc +(2k−1)ωo }|  × cos {2N mωc +(2k−1)ωo } t   imag [Gt j{2N mωc +(2k−1)ωo }] + tan . real [Gt j{2N mωc +(2k−1)ωo }] −1 (6) Therefore, the final expression for switching function se may be obtained by adding (5) and (6) as se (t) = mse (t) + sse (t). (7) Consider the representation of the lth triangular carrier in terms of the unit triangular signal ∆(·) and the corresponding Fourier GUPTA et al.: SWITCHING CHARACTERIZATION OF CASCADED MULTILEVEL-INVERTER-CONTROLLED SYSTEMS 1051 modulation. Also, the PWM signal for each leg is shifted by (ϕ/ωc ) at the instants of switching transitions tzc due to the presence of ripples and hysteresis band, where ϕ is defined as the leading displacement angle in radians of the PWM signal of each leg with respect to the ideal PWM. This is shown in Fig. 5(b) for five-level modulation. The figure shows the enlarged view of Fig. 5(a) with positive switching function and gating signal for the switch Sw11 . The peak of the ripples occurs at the instant (tzc − ϕ/ωc ). The displacement angle ϕ may be also considered as the relative lagging angle of the triangular carrier to generate the same output (4) and ripple peak from (7), all aligned at the instants of switching transitions tzc of the ideal PWM. However, this displacement angle ϕ is variable and depends on the position of ripples in (7) and hysteresis band h at the switching transition instants tzc . The use of larger amplitude of carrier increases the amplitude of the modulating signal (5). This decreases the ratio of ripple to modulating signal, and, hence, the angle ϕ approaches zero. However, it will be shown in the following section that the large amplitude of carrier decreases the forward gain and, hence, deteriorates the tracking characteristics. Therefore, there is a need to obtain the minimum amplitude of the carrier that will provide the fixed switching frequency smooth modulation. Switching Transition Instants tzc : Switching transition instants tzc for the multilevel modulation are defined as the time instants of the intersection of the ideal switching function and the triangular carrier, as shown in Fig. 5(b). For multilevel inverters with N number of carriers, the total number of switching transition instants using all N carriers is 2N (2ωc /ωo ) over one cycle of the fundamental period To (= 2π/ωo ). These switching transition instants t = tzc can be numerically determined by solving the following: ±Mi cos(ωo t) − ∆ (ωc t + (l − 1)π/N ) = 0. Fig. 5. (a) Modulation of H-bridge 1 using ideal switching function. (b) Effect of switching ripples on switching transitions for the five-level modulation. series representation as   (l − 1)π vtri l (t) = Vtri ∆ ωc t + N  ∞ cos p ωc t + π +
8Vtri = 2 π p2 (l−1)π N . (8) p=1(2) For ideal switching function (5) and h = 0, the PWM output (4) is generated with the carrier represented by (8). Fig. 5(a) shows the modulation of H-bridge 1, gating signals, and the three-level output of the H-bridge 1 under this ideal condition. Similarly, other H-bridges will be also modulated with appropriate phase shift of the carrier. Adding outputs of the N cascaded H-bridges will produce n-level output. Under this ideal condition, an arbitrarily small amplitude of the carrier may be used, and this leads to a large gain in the forward path, as will be shown in the following section. However, the presence of ripples in the actual switching function (7) limits the amplitude of the carrier to a minimum value for smooth (9) The solution of (9) implies monitoring the instant tzc at which the left-hand side (LHS) of (9) changes its sign with increasing t. Proposition 1: The amplitude of the triangular carrier under smooth modulation of multilevel inverters with N number of H-bridges in cascade satisfies the following relation: Vtri = ±h ± sse (tzc )  ±Mi cos(ωo tzc ) − ∆ ωc tzc − ϕ + (l−1)π N (10) where l = 1, 2, . . . , N . For each l, there are four conditions. For the lth index, the following will be used in (10): 1) −sse (tzc ), +h, and +Mi cos(ωo tzc ): The switching transition instants are determined from (9), considering +Mi cos(ωo tzc ) in (9) for the transition from negative to positive. 2) −sse (tzc ), −h, and +Mi cos(ωo tzc ): Same as condition 1 for the transition from positive to negative. 3) +sse (tzc ), +h, and −Mi cos(ωo tzc ): The switching transition instants are determined from (9), considering −Mi cos(ωo tzc ) in (9) for the transition from negative to positive. 1052 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 3, MARCH 2008 4) +sse (tzc ), −h, and −Mi cos(ωo tzc ): Same as condition 3 for the transition from positive to negative. Proof: For an n-level inverter, there will be N carriers corresponding to N H-bridges. The lth carrier is phase shifted by an angle (l − 1) π/N . Each transition in the multilevel output (4) from one level to next level can be determined using (9) corresponding to the respective phase shift in modulating signal and carrier. From switching condition (3.1a), the switching transition of the PWM output of the first leg of the lth H-bridge will follow the intersection of the lth carrier with the switching function se (t) and delayed by +h. Considering the lagging displacement angle ϕ at the zero-crossing instant tzc of the triangular carrier, the following is satisfied:   (l − 1)π se (tzc ) − Vtri ∆ ωc tzc − ϕ + = +h. (11) N having small variation in ϕ over one cycle of the fundamental frequency. The average of these values, i.e., ϕav , gives a good estimate of the displacement angle due to the presence of ripples and hysteresis band. Fig. 6 shows the flowchart for the determination of tzc , Vtri min , and ϕav . The two variables tzc and ϕ are shown as an array in the flowchart to represent their multiple values. To determine tzc , the sign change in the LHS of (9) should be checked as discussed earlier. For obtaining ϕ from (12), a suitably small tolerance should be considered to avoid exact equality. The variable ϕj is an intermediate value of ϕ in the flowchart. The determination of ϕav is just of theoretical interest. For practical implementation, determining Vtri min is an important requirement that also requires tzc to be calculated. Furthermore, substitute mse (t) from (5) into (7) and then se (t) from (7) in (11) at t = tzc . Now, by deriving the expression for Vtri using (11), condition 1 given above is proved. Similarly, conditions 2–4 can be proved using switching conditions (3.1b), (3.2a), and (3.2b), respectively.
However, it is difficult to determine the triangular carrier amplitude Vtri using (10) for smooth modulation, as the righthand side (RHS) of (10) contains an unknown term ϕ and is variable even for fixed Vtri . The following approach is proposed to calculate Vtri and ϕ. This also gives an approximately close result for the minimum value of Vtri . The expression for ∆(·) can be rearranged from (10) as follows:   (l−1)π ±h ± sse (tzc ) ∆ ωc tzc −ϕ+ . = ±Mi cos(ωo tzc )− N Vtri (12) The modulation index Mi attained by the modulator under closed loop in the steady state is not a priori known. This depends on the operating conditions, e.g., the value of the tracking reference, the source voltage, the loading condition, etc., and varies from 0 to 1 for the fixed switching frequency operation. Overmodulation, i.e., Mi > 1, leads to the no-switching condition for certain duration. This distorts the output waveform. Therefore, the operation of the modulator is considered in the range 0 < Mi < 1. Remark 2: For the determination of the minimum amplitude of the carrier from (13), the maximum value of the modulation index Mi max should be used. This is because modulating signal (5) assumes maximum variation in the switching function for Mi max , and, therefore, the slope of the ripples in the switching function will also have maximum variation. Moreover, the highest level of uo , i.e., +1 and −1, will disappear for a lower modulation index due to the unipolar nature of the modulation. Therefore, (13) will give a better result for Mi close to unity. However, the presence of ripples in the switching function restricts the use of the maximum modulation index Mi = 1. This is because the peak of the switching function grazes the upper or lower tip of the carrier due to the presence of ripples. The achievable Mi max approaches unity with an increase in the number of levels for fixed carrier frequency fc due to the decreased amplitude of ripples. Therefore, for higher inverter levels, the usable Mi max will be higher, and the actual switching function approaches the ideal one. Mi max starting from 0.8 to 1.0 should be used in (13). Once the amplitude of the carrier is determined on the basis of the maximum modulation index, then, under all operating conditions, the multilevel modulation will be smooth as long as 0 < Mi < Mi max . In order that the solution of (12) exists for smooth modulation, the absolute value of the RHS of (12), which represents the normalized peak value of the ripple at the switching transition instant tzc , should be less than the unity evaluated for all 2N (2ωc /ωo ) instants. If at any instant of tzc , this peak value exceeds unity, then (12) cannot be satisfied with unit triangular signal ∆(·) for any value of ϕ, and the slope of the ripple exceeds the slope of the carrier. Therefore, the condition of smooth modulation may be written as ±Mi cos(ωo tzc ) − ±h ± sse (tzc ) <1 Vtri ∀t = tzc . (13) Remark 1: The minimum amplitude Vtri min can be determined using (13). The amplitude Vtri is reduced in the fixed step until (13) is satisfied for all the zero crossing instants tzc . The critical value obtained is denoted as Vtri min . It may be noted that the correct combination of signs should be used in (13), as given in Proposition 1, and the corresponding tzc should be determined using (9). For smooth modulation at fixed switching frequency, the triangular carrier is chosen with the amplitude greater than or equal to the minimum calculated as above. To calculate the angle ϕ, (12) may be numerically solved for each Vtri . The angle ϕ is variable even for a fixed Vtri , as seen from Fig. 5(b), and this led to the solution of (12) B. Choice of Modulation Index C. Low-Frequency Gain of the Modulator The carrier-based modulator M shown in Fig. 3 may be represented by a constant gain for low-frequency signals, the value of which depends on the carrier amplitude. For calculating lowfrequency gain, high-frequency switching components, i.e., the second term in (4), are ignored. The input to the modulator is the low-frequency modulating signal (5). The output of the modulator is the first term of the normalized PWM output of GUPTA et al.: SWITCHING CHARACTERIZATION OF CASCADED MULTILEVEL-INVERTER-CONTROLLED SYSTEMS Fig. 6. 1053 Flowchart for determination of (a) switching transition instants tzc , (b) minimum carrier amplitude Vtri min , and (c) average displacement angle ϕav . (4). Therefore, the low-frequency gain g of the modulator is the ratio of the output to the input as g= 1 Mi cos(ωo t) = . Vtri Mi cos(ωo t) Vtri (14) The modulator gain g increases with the increase in the levels of the inverter due to the decrease in the minimum carrier amplitude requirement Vtri min for higher levels at fixed frequency of the carrier. V. M ULTILEVEL M ODULATION OF DSTATCOM For multilevel modulation of DSTATCOM, each leg of the H-bridge follows the two-level carrier-based sliding mode control (3), each shifted in definite time instants leading to multiple levels. The stability for tracking of low-frequency reference for small perturbations can be tested using modulator gain (14) in the forward path of the resultant closed loop system. In this section, switching conditions for the multilevel modulation of DSTATCOM are obtained, and the amplitude of the triangular carrier is determined for smooth modulation of three- and fivelevel inverters using condition (13). Fig. 7 shows the block diagram for multilevel modulation and control of DSTATCOM. For calculation of triangular amplitude using (13), the source Fig. 7. Block diagram of multilevel modulation and control of DSTATCOM. vs and the periodic voltage vd are considered zero in Fig. 7, as these are external sources and do not carry any switching components. Therefore, in steady state, the block diagram of Fig. 7 will be reduced to Fig. 3. The controller transfer function Gc (s) using (2) and the system transfer function G(s) between vt and uo can be obtained using (1) as G(s) = c(sI − A)−1 b2 , Gc (s) = (k1 s + k2 ). (15) Consider the system parameters given in Appendix II. The transfer function G(s) is determined. The control of the DSTATCOM is compared with the three- and five-level modulations using the cascaded inverter topology given in Section III. A carrier frequency of 1.0 kHz is considered for the modulation of three- and five-level inverters. 1054 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 3, MARCH 2008 TABLE I EFFECT OF CARRIER AMPLITUDE ON VARIOUS CHARACTERISTICS FOR T HREE - AND F IVE -L EVEL I NVERTERS Let time constant T = 0.4 ms be chosen with k1 = 0.001 s and k2 = 2.5. The minimum amplitude for the triangular carrier Vtri min is calculated as 41.0 and 17.0 V for three- and five-level modulations, respectively, using the process given in the flowchart of Fig. 6(b). The value of the hysteresis band considered is h = 0.5 V. Calculation of Vtri is done in the fixed step of ∆Vtri = 1.0 V. A time step of ∆t = 10.0 µs is considered for calculating switching transition instants tzc using the flowchart of Fig. 6(a). The modulation index Mi = 0.8 and Mi = 0.9 is considered for three- and five-level inverters, respectively, for the purpose of determining Vtri as discussed in Remark 2. Infinite series (6) is terminated with the indexes m = 60 and k = 15. Table I shows the average value of displacement angle ϕav obtained for different values of Vtri using the process described in Fig. 6(c) with ∆ϕ = 0.1◦ . ϕav decreases with an increase in the carrier amplitude Vtri . The carrier amplitudes shown in the first rows of Table I are the minimum amplitudes Vtri min . A sinusoidal reference is used for the PCC voltage with an rms value of 60.0 V that lags the source voltage by an angle δ = −20◦ . The steady-state tracking errors and closed loop poles need to be estimated for each Vtri . In addition to the forward gain g, the multilevel modulator also offers an average switching delay Td = 1/(2N fc ), where 2N fc is the effective switching frequency in the multilevel output uo due to the harmonic cancellation of the lower switching components from (4). In frequency domain, this delay is represented by Gd (s) = 1/(1 + sTd /2). The net loop transfer function is obtained as gGc (s)Gd (s)G(s) and used for the purpose of stability studies under closed loop. The absolute value of the following expression gives an approximate estimate of the peak of the tracking error at the fundamental frequency (ωo = 314 rad/s): e(jωo ) = |Vtref |(cos δ + j sin δ) − |Vs |Gs (jωo ) 1 + gGc (jωo )Gd (jωo )G(jωo ) (16) where Vtref and Vs are the peak of the reference terminal voltage and source voltage, respectively, and Gs (s) = c(sI − A)−1 b1 . Table I also lists the dominant closed loop poles and TABLE II (a) MINIMUM AMPLITUDE OF CARRIER Vtri min (IN VOLTS); (b) TRACKING ERROR IN VOLTS (rms) tracking error at different values of carrier amplitudes for threeand five-level inverters. Note that the periodic voltage source vd is neglected, and the source voltage vs is considered sinusoidal while estimating the tracking error. The tracking error decreases for five-level inverters due to the higher gain g. The stability properties also improve for five-level inverters due to the higher gain g and reduced switching delay Td . This, in effect, also improves the bandwidth of the control loop. Both tracking error and stability properties are best at the minimum carrier amplitude Vtri min . Remark 3: Any attempt of using an additional low-pass filter in the forward path of Fig. 7 to attenuate high-frequency ripples will deteriorate the control and tracking performance [7] due to the inherent phase delay involved with such filters. This is more important for higher order circuits like DSTATCOM represented by (1). However, if the harmonic cancellation of multilevel inverters is well above the control bandwidth, and one uses such low-pass filters, it can be combined with Gc (s) and follow the analysis described above. VI. S IMULATION R ESULTS In this section, simulation is performed for the proposed DSTATCOM control and modulation. Controller parameters and references are the same as those used in Section V. The results are obtained using the power systems CAD/ electromagnetic transients including DC (PSCAD/EMTDC) simulation package with the simulation time step of 10 µs. The nonlinear load connected in the system of Fig. 1 consists of a full-bridge diode rectifier with equivalent dc side resistance of 20.0 Ω and a parallel dc capacitor of 440 µF. The source voltage considered is nonideal with the total harmonic distortion (THD) of 5.86%. The THD of the uncompensated PCC voltage is 20.32%. Consider the system parameters given in Appendix II. The minimum carrier amplitudes obtained for smooth modulations through simulations are given in Table II(a) for three- and fivelevel inverters. These are close to the theoretical estimated values of Vtri min . The use of input impedance (Ll , Rl ) smoothens the nonlinear effect of the load such that the modulating signal in the switching function is close to sinusoidal. Simulation is performed at the minimum amplitudes of the carrier. Fig. 8 shows the tracking of the PCC voltage to the corresponding reference along with the tracking errors for three- and five-level controls, respectively. The THD of the PCC voltage is improved to 1.6% and 0.5% with three- and five-level controls, respectively. The improved GUPTA et al.: SWITCHING CHARACTERIZATION OF CASCADED MULTILEVEL-INVERTER-CONTROLLED SYSTEMS 1055 Fig. 9. Uncompensated PCC voltage; scale 1 V : 50 V. Fig. 8. PCC-controlled voltage, reference voltage, and tracking error (simulation results) for (a) three-level inverter and (b) five-level inverter. performance for the five-level control is due to the better harmonic cancellation and higher bandwidth discussed earlier. The rms values of the tracking errors are shown in Table II(b). These are close to those theoretically estimated. The THD measured for the load current is 16.0%, and that is improved to 4.5% for the source current with a five-level control. The detailed results are shown in Section VII. VII. E XPERIMENTAL R ESULTS A laboratory model of the single-phase DSTATCOM is implemented with the parameters given in Appendix II. The nonlinear load, source, references, and controller parameters are same as those considered in Section VI. A field-programmable gate array (FPGA) based controller is used for the modulation and control of the multilevel inverters. The controller is implemented using NI LabVIEW FPGA module programming that runs on reconfigurable I/O NI 7831R embedded in a remote PXI 8186 processor. The H-bridges of the multilevel inverters are implemented using two arms of the Intelligent Power Modules PM50CSD120. The terminal voltage and the filter capacitor current are fed back using the voltage and current transducers LV 25-P and LA 55-P, respectively. The FPGA executes the following control loop in parallel: 1) generation of gating signals for different switches of the cascaded H-bridges; 2) reference generation using software-based phase-locked loop; and 3) inserting dead time in the gating of the complementary switches of the same arm. The loop delay of 10 µs is used to account for signal conversion and computation time. The uncompensated distorted PCC voltage is shown in Fig. 9. The experimental result for the three-level control of the DSTATCOM is shown in Fig. 10. The switching signals of 1.0 kHz are generated by FPGA after smooth modulation of the switching function using the triangular carrier. The gating of the switch Sw11 is shown in Fig. 10(a). The signal obtained from the digital output of NI 7831R corresponds to TTLcompatible voltage levels of 0.0 and 3.3 V and is used for the gating of the IGBT. The switching signals for other switches are similar except that they are shifted in the corresponding phase. Fig. 10(b) and (c) shows the voltage tracking error and the PCCcontrolled voltage, respectively. Both waveforms show a ripple frequency of 2.0 kHz, which clearly indicates the cancellation of harmonics up to 2.0 kHz for the three-level inverter. The distorted source voltage is shown in Fig. 10(d). The three-level inverter output voltage is shown in Fig. 10(e). Corresponding results for the five-level control are shown in Fig. 11. It is clear from Fig. 11(b) and (c) that the ripple frequency is 4.0 kHz, which indicates the harmonic cancellation up to 4.0 kHz for the five-level modulation. Fig. 11(f) shows the five-level inverter output voltage along with the individual three-level output of two-cascaded H-bridges shown in Fig. 11(e) and (g). The voltage across each H-bridge is half of that for the case of the three-level inverter. The minimum amplitude of the carrier at which the smooth modulations of Figs. 10 and 11 are obtained is given in Table II(a). These amplitudes are slightly higher as compared to those obtained from the simulation due to the presence of noise in the switching function. The carrier amplitudes shown in Table II(a) are realized at the reduced scale of 1/50 in the digital processor to make it compatible with the scaled switching function. The tracking errors approximately calculated are given in Table II(b). Increased values in error are due to the reduced modulator gain at higher carrier amplitude and other experimental errors. The distorted load current and improved source currents are shown in Fig. 11(h) and (i), respectively, with the five-level 1056 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 3, MARCH 2008 Fig. 10. Three-level control (experimental result). (a) Gating signal for Sw11 . (b) Tracking error; scale 1 V : 50 V. (c) PCC-controlled voltage; scale 1 V : 50 V. (d) Source voltage; scale 1 V : 120 V. (e) Three-level inverter output voltage; scale 1 V : 100 V. Fig. 11. Five-level control (experimental result). (a) Gating signal for Sw11 . (b) Tracking error; scale 1 V : 50 V. (c) PCC-controlled voltage; scale 1 V : 50 V. (d) Source voltage; scale 1 V : 120 V. (e) Three-level output voltage of H-bridge 1. (f) Five-level output of the two cascaded H-bridges. (g) Three-level output voltage of H-bridge 2. The scale is 1 V : 100 V for (e)–(g). (h) Load current and (i) source current with the five-level control [scale 1 V : 2.5 A for (h) and (i)]. control. The improvement in the THD for the PCC voltage and the source current is similar to that obtained in the previous section. The performance of the five-level control against sag and swell is shown in Fig. 12. The PCC voltage is controlled to the fixed reference in case of sag and swell in the source voltage. GUPTA et al.: SWITCHING CHARACTERIZATION OF CASCADED MULTILEVEL-INVERTER-CONTROLLED SYSTEMS 1057 Fig. 12. Compensating performance of DSTATCOM with the five-level control. (a) Sag and (b) swell in the source voltage. Scale 1 V : 50 V. Remark 4: In this paper, the proposed multilevel modulation and control are verified for the low-voltage distribution system model. However, these can be applied to any medium-voltage distribution system with suitable cascaded multilevel topology. If comparison is made with the conventional two-level inverters, the performance with carrier frequency of 1.0 kHz leads to the tracking error of 14.0 V (rms) and the THD of the PCC voltage as 9.5%. To achieve performance that is close to that of five-level inverters, carrier frequency of at least 4.0 kHz or higher is required. Also, the quality of the output voltage for the multilevel inverters is much improved as compared to that for the two-level inverters [19]. On comparing losses in the VSIs, it is known that the total loss in the inverter circuit consists of switching loss and conduction loss [16]. If the loss comparison is made with reference to the application at a medium-voltage distribution system, the switching losses with the two-level inverters are significantly high on account of high switching frequency and high switching loss energies, with higher rated devices needed for the two-level inverters [20]. It is shown in [20] that the total semiconductor loss will be higher for the two-level inverters, although the conduction loss would be high for higher level inverters, and that too concentrated in fewer devices for the two-level inverters. Similar comparison can be made between three- and five-level inverters. TABLE III SYSTEM PARAMETERS A PPENDIX I S YSTEM M ATRICES  s −R Ls   Rs − RT L LT A=  s  0 bT2 = [ 0 bT3 = [ −1 Ll 1 Ls Vdc LT 1 Ll 1 Ls + L1l  1 1 1 T −R − LT Ls + LT + Ll 1 Cf 0 0 1 Ll 0 bT1 = [ − L1s  0 0 0]  Rs Ls l −R Ll    Rl  s −R + Ls Ll    0 l −R Ll 0 0] 0 −1 Ll ]. VIII. C ONCLUSION The condition of smooth modulation for the multilevelinverter-controlled system has been obtained. A method has been developed for the determination of the minimum amplitude of the triangular carrier. The modulation follows the harmonic cancellation properties of the phase-shifted multicarrier unipolar PWM. The performance is best near the minimum amplitude of the carrier. Also, for a fixed frequency carrier, the overall performance improves with an increase in the level of the inverter. These include improvement in tracking characteristics, bandwidth, achievable modulation index, etc. The modulation condition that has been developed is justified for the system having filtering of the higher order harmonic components of the load and source. Both simulation and experiment validate the theoretical results. The FPGA-based implementation of DSTATCOM control gives close approximation to both theoretical and simulation results. A PPENDIX II The system parameters are listed in Table III. R EFERENCES [1] J. Rodriguez, J. S. Lai, and F. Z. Peng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724–738, Aug. 2002. [2] D. G. Holmes and B. P. McGrath, “Opportunities for harmonic cancellation with carrier-based PWM for a two-level and multilevel cascaded inverters,” IEEE Trans. Ind. Appl., vol. 37, no. 2, pp. 574–582, Mar./Apr. 2001. [3] F. Z. Peng, J. W. McKeever, and D. J. Adams, “A power line conditioner using cascade multilevel inverters for distribution systems,” IEEE Trans. Ind. Appl., vol. 34, no. 6, pp. 1293–1298, Nov./Dec. 1998. [4] R. Gupta, A. Ghosh, and A. Joshi, “Cascaded multilevel control of DSTATCOM using multiband hysteresis modulation,” IEEE Power Eng. Soc. General Meeting 2006, Jun. 18–22, 2006. 1058 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 3, MARCH 2008 [5] M. P. Kazmierkowski and M. A. Dzieniakowski, “Review of current regulation methods for VS-PWM inverters,” in Proc. IEEE Int. Symp. Ind. Electron., Jun. 1–3, 1993, pp. 448–456. [6] R. Gupta and A. Ghosh, “Frequency-domain characterization of sliding mode control of an inverter used in DSTATCOM application,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 3, pp. 662–676, Mar. 2006. [7] S. Buso, L. Malesani, and P. Mattavelli, “Comparison of current control techniques for active filter applications,” IEEE Trans. Ind. Electron., vol. 45, no. 5, pp. 722–729, Oct. 1998. [8] M. P. Kazmierkowski and L. Malesani, “Current control techniques for three-phase voltage-source PWM converters: A survey,” IEEE Trans. Ind. Electron., vol. 45, no. 5, pp. 691–703, Oct. 1998. [9] B. Nicolas, M. Fadel, and Y. Cheron, “Fixed-frequency sliding mode control of a single-phase voltage source inverter with input filter,” in Proc. IEEE Int. Symp. Ind. Electron., Jun. 17–20, 1996, vol. 1, pp. 470–475. [10] A. Cataliotti, F. Genduso, A. Raciti, and G. R. Galluzzo, “Generalized PWM–VSI control algorithm based on a universal duty-cycle expression: Theoretical analysis, simulation results, and experimental validations,” IEEE Trans. Ind. Electron., vol. 54, no. 3, pp. 1569–1580, Jun. 2007. [11] M. Aime, G. Gateau, and T. A. Meynard, “Implementation of a peakcurrent-control algorithm within a field-programmable gate array,” IEEE Trans. Ind. Electron., vol. 54, no. 1, pp. 406–418, Feb. 2007. [12] A. K. Gupta and A. M. Khambadkone, “A space vector PWM scheme for multilevel inverters based on two-level space vector PWM,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1631–1639, Oct. 2006. [13] M. K. Mishra, A. Ghosh, and A. Joshi, “Operation of a DSTATCOM in voltage control mode,” IEEE Trans. Power Del., vol. 18, no. 1, pp. 258– 264, Jan. 2003. [14] F. Z. Peng, “Application issues of active power filters,” IEEE Ind. Appl. Mag., vol. 4, no. 5, pp. 21–30, Sep./Oct. 1998. [15] M. Carpita and M. Marchesoni, “Experimental study of a power conditioning system using sliding mode control,” IEEE Trans. Power Electron., vol. 11, no. 5, pp. 731–742, Sep. 1996. [16] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications, and Design. Singapore: Wiley, 1989. [17] D. G. Holmes and T. A. Lipo, Pulse Width Modulation for Power Converters. Piscataway, NJ: IEEE Press, 2003. [18] K. Ogata, Modern Control Engineering, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 1991. [19] M. E. Ortuzar, R. E. Carmi, J. W. Dixon, and L. Moran, “Voltage-source active power filter based on multilevel converter and ultracapacitor DC link,” IEEE Trans. Ind. Electron., vol. 53, no. 2, pp. 477–485, Apr. 2006. [20] R. Teichmann and S. Bernet, “A comparison of three-level converters versus two-level converters for low-voltage drives, traction, and utility applications,” IEEE Trans. Ind. Appl., vol. 41, no. 3, pp. 855–865, May/Jun. 2005. Rajesh Gupta (S’05) received the B.E. degree from Madan Mohan Malaviya Engineering College, Gorakhpur, India, in 1993, the M.E. degree from Birla Institute of Technology, Mesra, Ranchi, India, in 1995, and the Ph.D. degree from Indian Institute of Technology, Kanpur, India, in 2007, all in electrical engineering. From 1996 to 1999, he was a Lecturer with Govind Ballabh Pant Engineering College, Pauri Garhwal, India. He is currently a Senior Lecturer with the Department of Electrical Engineering, M. N. National Institute of Technology, Allahabad, India. His interests include control of power electronics based systems, multilevel converters, theoretical control, and systems dynamics. Dr. Gupta is a First Prize Winner of the VI Mantra 2006 contest organized by National Instruments, India, for his work on FPGA control of multilevel converters. Arindam Ghosh (S’80–M’83–SM’93–F’06) received the Ph.D. degree in electrical engineering from the University of Calgary, Calgary, AB, Canada, in 1983. He was with Indian Institute of Technology, Kanpur, India, for 21 years. He is currently a Professor of Power Engineering with Queensland University of Technology, Brisbane, Australia. He has been a Fulbright Scholar with the University of Illinois, Urbana-Champaign. His interests include control of power systems and power electronic devices. Dr. Ghosh is a Fellow of Indian National Academy of Engineering. Avinash Joshi received the Ph.D. degree in electrical engineering from the University of Toronto, Toronto, ON, Canada, in 1979. From 1970 to 1973, he was with The General Electric Company (GEC) of India Limited, Calcutta, India. He is currently a Professor of electrical engineering with Indian Institute of Technology, Kanpur, India. His interests include power electronics, circuits, digital electronics, and microprocessor systems.