Lehigh Preserve Institutional Repository A model for optimizing a digital bipolar integrated circuit process. Koons, Frederick J. 1984 Find more at https://preserve.lib.lehigh.edu/ This document is brought to you for free and open access by Lehigh Preserve. It has been accepted for inclusion by an authorized administrator of Lehigh Preserve. For more information, please contact preserve@lehigh.edu. A MODEL FOR OPTIMIZING A DIGITAL BIPOLAR INTEGRATED CIRCUIT PROCESS by Frederick J. Koons A Thesis Presented to the Graduate Committee of Lehigh University in Candidacy for the Degree of Master of Science in Electrical Engineering Lehigh University 1984 © 1984, AT4T TECHNOLOGIES, INC. ProQuest Number: EP76515 All rights reserved INFORMATION TO ALL USERS The quality of this reproduction is dependent upon the quality of the copy submitted. In the unlikely event that the author did not send a complete manuscript and there are missing pages, these will be noted. Also, if material had to be removed, a note will indicate the deletion. uest ProQuest EP76515 Published by ProQuest LLC (2015). Copyright of the Dissertation is held by the Author. All rights reserved. This work is protected against unauthorized copying under Title 17, United States Code Microform Edition © ProQuest LLC. ProQuest LLC. 789 East Eisenhower Parkway P.O. Box 1346 Ann Arbor, Ml 48106-1346 This thesis is accepted and approved in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering. date) 7 Professor*/ in Cnarge Chairman of Department - 11 - a-*1! ACKNOWLEDGEMENTS The writer would like to express his appreciation to the following people for their contributions to this work: R. J. Chin, Monolithic Memories, Inc. P. A. Gillespie, AT&T Technologies, Inc. R. J. Jaccodine, Lehigh University Ann Koons, Bethlehem, PA W. A. Possanza, AT&T Technologies, Inc. iii TABLE OF CONTENTS Page? Ti tl e Page i Certificate of Approval ii Acknowledgements Tabl e of Contents iii .> iv List of Figures vi Abstract 1 1.0 Introduction 3 1.1 Parametric Yield Improvement 4 1.2 Model Development 7 1.3 Methodology 8 1.4 The Transistor 9 1.5 Emitter Push 9 1.6 Diffusion Process 12 1.7 Measurements 13 2.0 3.0 Diffusion Model !... 16 2.1 Base Analysis 17 2.2 Emitter Diffusion Analysis 25 2.3 Pinch Sheet Resistance 26 2.4 Emitter Push Analysis 27 Transistor Model 30 3.1 30 Gain Analysis iv - TABLE OF CONTENTS (Continued) 4.0 5.0 Sheet Resistance Coorelatlons 34 4.1 Emitter Sheet Resistance 35 4.2 Base Sheet Resistance 35 4.3 Pinch Sheet Resistance 36 Discussion 37 5.1 Speed Characteristics 37 5.2 Voltage Breakdown Characteristics 38 5.3 Summary „. 40 References 42 Appendix I 44 Appendix II 46 Appendix III ..." 47 Appendix IV 49 Appendix V 51 Figures 52 VITA 86 y _ '""*'■•.._ ... _ ,_^'~"~ LIST OF FIGURES Figure 1 - Categorization of Model Parameters Figure 2 - Schematic Representation of a Bipolar Junction Transistor Showing the Emitter Push and Other Spatial Design Parameters Figure 3 - Outline of a Standard Buried Collector Process Figure 4 - Phosphorous Profile Showing the According to the Fair-Tsai Model Figure 5 - Interrelationship of the Diffusion Model Parameters Figure 6 - Sheet Resistance Patterns Figure 7 - Logical,,Development of the Diffusion Model Figure 8 - Logical Development of the Base Analysis Figure 9 - Distributions of Control Wafer Readings Generation of Vacancies Figure 10 - Extrapolation of the Solid Solubility Curve for Boron in Silicon Figure 11 - Approximation for the Irvin p-type ERFC Profile Figure 12 - Approximation for the ERFC Curve Figure 13 - Diffusivity of Boron in Silicon Figure 14 - Approximation for the Gaussian Curve Figure 15 - Approximation for the Irvin, p-type Gaussian Profile Figure 16 - Schematic Representation of Diffusion Profiles Figure 17 - Calculated Values of Base Sheet Resistance as a Function of the Base-Collector Junction Depth Figure 18 - Approximation for the Irvin Curve, n-type ERFC Figure 19 - Plot of Control Wafer Emitter Sheet Resistance versus Emitter Diffusion Time Figure 20 - Approximation for the Irvin Curve, n-type, ERFC - VI LIST OF FIGURES (Continued) Figure 21 - Pinch Sheet Resistance as a Function of Base Width Figure 22 - Logical Development of the Emitter Push Derivation Figure 23 - Plot of Calculated Values of Emitter Push versus Emitter Diffusion Time Figure 24 - Plot of Enhancement Factor versus Emitter Diffusion Time Figure 25 - Equivalent Circuit for a Bifurcated Transistor Figure 26 - Logical Development of*1 the Gain Derivation Figure 27 - Gain as a Function of Lateral Base Width Figure 28 - Emitter Sheet Resistance - CATS versus In-Process Figure 29 - Base Sheet Resistance - CATS versus In-Process Figure 30 - Pinch Sheet Resistance - CATS versus In-Process Figure 31 - Pinch Sheet Resistance Measurements Figure 32 - Gain to Pinch Ratio versus Lateral Base Width Figure 33 - Breakdown Voltage versus Gain - vii - ABSTRACT Models, including circuit analysis models such as SPICE [3], device models such as Gummel-Poon [5], and process models such as SUPREME [6], were developed to aid in the design of devices and processes. quently, to be useful Conse- they must be applicable over a wide range of design parameters and operating conditions. Such generality makes it too difficult to link device and process models. The purpose of the model developed in this thesis, on the other hand, is to increase the understanding of a particular device within a narrow range of design and operation in order to improve yield. Therefore, a different methodology is used which simplifies the problem and allows linking of the device characteristics to the process variables. The model focuses on the effect of emitter push and extends the work done by R. J. Chin [1] into the normal design scheme for a bipolar transistor. Chin observed that for a sevice with a large emitter push for which the emitter junction depth is greater than the original basecollector depth, a shift in gain occurs. This is explained by consider- ing two distinct base widths, the normal vertical one, W , and a lateral one, W.. In this thesis, the bifurcation effect is introduced. The bi- furcation effect is the splitting of the base current into two separate components by the perturbation in the base-collector junction which occurs because of emitter push. This effect is modelled by a formula for gain as a function of the two base widths postulated by Chin. 1 - In addition, calculation of W a diffusion and W. model is developed which allows the from easily measured sheet resistance measurements and process variables. Although the model applies only to a particular device made using specific conditions, the methodology used to develop it 1s of general application. 1.0 INTRODUCTION It is common practice to test an integrated circuit before the wafer is separated into chips. Contact is made to the input and output leads using a probe and a series of tests is made. which passes all of the tests. A "good" chip is one The probe yield, i.e., the ratio of good chips to the total tested is the dominant factor in the cost of producing integrated circuits. Yield improvement, an important economic consideration, is aimed at improving this ratio. For a digital bipolar integrated circuit there are two categories of tests - functional and parametric. the entire circuit is tested. A functional test is one in which A series of l's and 0's is applied to the input leads, and responses which are specified in a truth table are read on the output leads. electrical failure. A defect anywhere on the chip can result in an If the chip is defect-free and the circuit responds in accordance with the truth table, the chip is said to be "functional". Functional chips are then subjected to a series of "parametric" tests on each input and output in order to guarantee that the circuit is compatible with other parts in a larger system. Parametric testing ensures that the chip functions at specified levels of speed, power, fan-in, fan-out, and noise margin. Generally, the mechanisms causing functional failure are different from those causing parametric failures. Functional failures are usually due to discrete defects; parametric failures are usually due to defects which extend over a large part of the wafer. Thus, functional failures are randomly distributed; parametric failures occur in clusters. - 3 - ,) Because of the difference in failure mechanisms, improvement of functional yields calls for a different type of engineering activity than does the improvement of parametric yields. To maximize the functional yield, defect densities must be reduced and engineering is focused on cleanliness and improvement of processing methods. To maximize the parametric yield, on the other hand, major variables must be identified, their relationships defined, and controls introduced. • The model developed 1n this thesis 1s Intended as an aid to the engineer for the Improvement of parametric yields, a more subtle and difficult task. f 1.1 Parametric Yield Improvement Moreso than in the case of functional yields, improvement of para- metric yields demands an understanding of device and processing theory. Each of the basic elements on a bipolar integrated circuit - Schottky diodes, resistors, and junction transistors has a different effect on parametric yield. In general, each leads to a different area of inves- tigation: (a) Junction leakage current, the most sensitive Schottky diode characteristic depends primarily on the integrity of the metallization process. (b) Resistance is affected largely by the line widths which depend on photolithographic exposure and processing. (c) Gain, the primary control parameter, for the transistor element depends strongly on pinch sheet resistance which is determined by the diffusion process. In effect, the three elements generate parallel lines of investigation which in a way define the scope of an engineer's "parametric yield activity". For each line of investigation, one must also develop a depth of understanding for a series of relationships extending from the basic process variables to the final test parameters. The factors associated wi.th this series of relationships can be categorized for the transistor element as shown in figure 1. The engineering activities dealing with the relationships between categories are also shown. They are: (a) Compliance defines the relationships between circuit parameters (parametric tests) and the test specification (minimum and maximum values required by the user). (b) Circuit Characterization defines the relationships between the circuit parameters and the device characteristics (measurements such as gain made on individual elements fabricated on special test chips on each wafer). (c) Device Characterization defines the relationships between the device characteristics and design parameters. types of design parameters: There are three (1) physical design parameters are the basic material properties such as lifetime, band gap, and diffusivity; (2) technological design parameters are those characteristics imparted by the process such as junction depth, surface concentration, and impurity profile; and (3) electrical design parameters are measurements made on bulk properties such as sheet resistance. - 5 (d) Optimization defines the relationships between the design parameters and the process variables such as time and temperature. As implied by the compartmentalization in figure 1, 1n the industry at the present time, the engineering activities directed at the various interfaces are relatively independent of one another. Thus, the engi- neer engaged in the optimization of a diffusion process uses a design parameter such as pinch sheet resistance as his criterion for success. At the other end of the line of investigation the engineers engaged in circuit and device characterization evaluate their gain distributions as functions of the pinch sheet resistance. This fragmentation of activity tacitly assumes a single variable line of relationship: yield - gain pinch sheet resistance - process variables. The assumption is forced on us because no model exists which extends along the entire line of investigation from process variables to parametric yield. It is an extremely difficult task if one sticks to the current methods for developing models, i.e., methods which'are broad in scope. In this thesis a meth- odology is presented which simplifies the task. The result is a model which links the main device characteristic of the transistor element, gain, to the design parameters and the pertinent process variables as indicated by the dotted lines in figure 1. Although the model is appli- cable only to a particular set of conditions the methodology used to develop it is applicable in a general way. 6 - ft 1.2 Model Development For a digital bipolar integrated circuit, yields are maximized by controlling the gain, maximizing the speed and guaranteeing a minimum junction breakdown voltage. It is proposed that this is best accom- plished by taking advantage of the emitter push effect. Emitter push, shown schematically in figure 2 is a perturbation in the collector-base junction which can have a major effect on the transistor characteristics. It has been observed [1] that when the emitter junction overtakes the original collector-base junction, a condition called "push-through" by Chin, there is a large shift 1n the gain of the transistor. Chin explains this by postulating two spatially distinct base widths: W , the normal vertical base width, and W., the lateral base width. Before push through occurs, gain 1s determined by W ; after push through gain is determined by W.. In this thesis a different explanation is presented. It is proposed that the base current bifurcates, i.e., separates into two components. The bipolar transistor, then can be represented by a two transistor equivalent circuit, one transistor associated with W the other with W,. and W. and The gain can be modelled as a function of both W to produce a relationship which adequately explains the Chin observation. In addition, a diffusion model is developed which allows one to translate easily measured sheet resistances Into the spatial parameters W and W.. 7 - design 1.3 Methodology Existing models are based on design oriented methodologies. They aim for generality in order to provide understanding over a broad range of design rules and operating conditions. Basically", there are three types of models: (a) Circuit Simulation Models such as SLIC [2] or SPICE [3] are designed for circuit characterization modelling the interconnection of individual elements in order to predict circuit performance. (b) Device Models such as Ebers-Moll [4] or Gummel-Poon [5] are designed for device characterization in that they predict device characteristics as a function of design parameters. (c) Process Models such as SUPREME [6] is designed for optimizing diffusion processes in that it predicts impurity profiles as a function of process variables. Circuit models always include device models to describe the behavior of the circuit elements. For example, SPICE uses both the Gummel-Poon and the Ebers-Moll models to characterize the transistors in the circuit. models. Consequently, circuit models are linked with device Device models, on the other hand, have not been linked to process models. Because existing models are general in nature, linking device and process models has been too difficult. The existing models, are \/ery useful for designing circuits and devices and for developing processes to produce them. But once a prototype has been produced, the problem shifts to that of improving yields. be used for yield improvement. - 8 - The existing models cannot In order to develop a model which is useful for yield improvement, generality is sacrificed and the model is developed for a particular set of conditions. This allows us to assume that certain model parameters are constant and it allows us to approximate portions of general curves by straight lines. Such simplifying methods allow analytic treatment of problems which are otherwise too complex. 1.4 The Transistor The device studied in this paper is a five-micron design rule bipolar junction transistor. It 1s produced using the standard buried layer process outlined in figure 3. photolithographic masking, Standard methods of oxidation, and oxide etching are used to define the regions into which impurities are diffused. Contacts and intercon- nections are. made using a titanium, titanium-nitride, platimum, gold metallization system. The Increasing level of integration in the industry has led to the design of smaller and smaller transistors. As a result, junctions are shallower and the emitter push is now larger relative to the geometry of the device. Consequently, any model intended for small geometry devices must address the phenomenon of enhanced diffusivity which is the cause of emitter push. 1.5 Emitter Push Emitter push, which is shown schematically in figure 2, is a perturbation in the collector-base junction directly below the emitter diffused area resulting from an enhanced diffusion constant in a localized area. Enhanced diffusivity is a phenomenon which has been studied and reported extensively in the literature. Most studies focus on the mechanisms with little emphasis on the effect emitter push has on either diffusion control or transistor characteristics. In this paper these effects are the foundation on which the model is built. 1.5.1 Pertinent Conditions Emitter push has always been observed in double diffused junction transistors. A variety of mechanisms have been proposed to explain it. Although there is disagreement among the mechanism proponents, there is common agreement on the following observations which are summarized in Willoughby's article [7]: (a) The size of the impurity is not a factor since emitter push has been observed in sequential diffusion of boron/phosphorus, gallium/ phosphorus, boron/boron, and phosphorus/boron [8]. (b) Oxidation enhances emitter push [9,10,11]. (c) Normal concentrations of arsenic produce little or no push [12]. (d) The magnitude of the push depends on the temperature of the emitter-diffusion, impurity concentrations in both base and emitter, the collector junction depth, and the emitter diffusion time [13,14,15]. (e) Push occurs in ranges up to 30 microns [16]. 10 - 1.5.2 Mechanisms The subject transistor is fabricated using a boron diffused base and a phosphorus diffused emitter. emitter push. This combination exhibits a strong In the literature, a variety of conditions have been explored each adequately explained by a different mechanism. This leads one to believe, that to a large extent, several mechanisms are involved of which the one that dominates depends on the experimental conditions [17,18]. The most applicable explanation for the effect under the conditions studied in this paper is the Fair-Tsai Model [19]. 1.5.3 The Fair-Tsai Model The Fair-Tsai model associated with is based on the action of charged vacancies concentration profiles as illustrated in figure 4. Vacancies can occur in four states: a donor state (V ), a neutral state (V°), and two acceptor states (V~, V~). As phosphorous atoms enter the silicon surface, they combine with doubly charged vacancies: P+ + V= ~P+V= (1) Since the number of vacancies in the high concentration region depends on the square of the free electron concentration, (n): „= w _2 (2) ! + = 2 the doubly charged E-center (P V ) also has an n dependence. As the E- center (P V~) diffuses out of the high concentration region, it crosses the point where the electron concentration (n ) has a Fermi-level value e that is O.lleV below the conduction band, a level corresponding to the second acceptor level of the V~ vacancy. 11 At that point, the doubly charged E-center gives up an electron and becomes a singly-charged E-center: f. P+V= =^PV + e"'. „ (3) Because the binding energy of the P V" is lower than the P V~, dissociation occurs: P+V" ^=^= P+ + V" (4) The result 1s a generation of excess vacancies at n=n which then diffuse rapidly into the silicon causing an enhanced diffusivity and with it emitter push. 1.6 Diffusion Process As shown in figure 3, the integrated circuit is produced by first growing a 5 to 6 micron thick n-type epitaxial silicon layer on a p-type substrate Into which an antimony buried layer is implanted and drivenin. After Isolation and deep-collector diffusions, the collector-base junction is formed using a two-step boron diffusion. In this investi- gation two predeposition "conditions were used: A - at 870°C for 42 minutes and, B - at 875°C for 46 minutes. After glass removal, both o groups were driven-in at 1100°C for 88 minutes. A nominal 5000A of oxide was regrown in the base area, windows were opened, and phosphorus diffused at 950°C for a time sufficient to produce a desired pinch sheet resistance. After metallization, wafers were heat treated at 300°C in hydrogen in order to reduce surface recombination and stabilize gain. - 12 - 1.7 Measurements Figure 5 parameters is a and their schematic representation interrelationships. of the It is diffusion model presented here to illustrate the large number of factors involved in the model. distinction is made between the types of parameters. Also, As indicated by the boxes, circles, and triangles, there are three types: (1) physical and technological design parameters (circles), (2) electrical design parameters (triangles), and (3) process variables (boxes). The physical and technolegTcTr^ design parameters are difficult to measure, consequently, are Tiot very useful model. Inputs are better chosen from as Inputs 1n a practical the easily-measured process variables and electrical design parameters. For the most part, process variables are set at particular values and are assumed constant. The measurements used to develop the model, therefore, are basically sheet resistance measurements which are measured in three ways: (1) on control wafers, (2) on test patterns in-process, and (3) on metallized test patterns at the end of the process. 1.7.1 Control Wafer Measurements Two blank n-type wafers are included in each base predeposition run. Sheet resistance 1s measured using a standard four-point probe technique at the conclusion of the run. The same two wafers accompany the lot through the base drive-in cycle and the post boron oxidation. Sheet resistance is measured after each operation. Thus, the change in sheet resistance 1s monitored at three points 1n the base diffusion - 13 - cycle. In a similar way, p-type control wafers are included with the lot during the emitter diffusion for the purpose of measuring emitter sheet resistance. 1.7.2 In-Process Measurements On each wafer there are four or five special test sites containing transistors, resistors, diodes, and a variety of test patterns. Three types of test patterns (see figure 6) are used to make sheet resistance measurements. In-process sheet resistance is measured on the seahorse pattern Immediately prior to emitter diffusion, one reading per wafer, to provide the base sheet resistance data used to calculate the emitter diffusion time. The pinch resistor is measured after the emitter diffusion. 1.7.3 CATS Measurements The special integrated test circuit sites patterns are metallized in order to along with allow a the complete primary set of measurements to be made on a Computer A,ided Test System, CATS for short. Tests Include both sheet resistances and device characteristics. Sheet resistances are made on van der Paaw patterns, pinch sheet resistance on the metallized pinch resistor. 1.7.4 Symbol Conventions To distinguish between the different sheet resistance measurements, the following convention 1s used: - 14 - (a) A small r with a subscripted s followed by a second subscript Is used for control wafer measurements. (b) A small r with a single subscript Is used for 1n-process measurements. (c) A capital R with a single subscript is used for CATS measurements. . Following are all of the sheet resistance symbols used in this thesis: r - control wafer sheet resistance after base predep. r . - control wafer sheet resistance after dr1ve-1n r f - final control wafer sheet resistance r -„ se - emitter control wafer sheet resistance r. - in-process base sheet resistance r - in-process emitter sheet resistance r - in-process pinch sheet resistance R. - final base sheet resistance at CATS R - final emitter sheet resistance at CATS b R e P - pinch sheet resistance at CATS 15 - 2.0 DIFFUSION MODEL There are two reasons for developing a diffusion model: (a) To provide a means for controlling the diffusion. This means i that given a measured base sheet resistance on each wafer, r. , the model can be used to calculate an emitter diffusion time, t , which will produce a desired pinch sheet resistance r . (b) To provide a means for calculating values for the spatial design parameters (junction depths and base widths) from easily measured sheet resistances. I The model is developed heuristlcally, i.e., the form is derived from first order theory, Gaussian, Complementary Error Function (ERFC), and Irvin curves, and then is modified using empirical data. The Gaus- sian and ERFC are well known solutions to Fick's diffusion laws. The Gaussian is the solution for a finite source of impurities; ERFC is the solution for a continuous source. Irvin's curves [20] are numerically calculated conductivities of diffused layers for both p and n-type, ERFC and Gaussian profiles for various background concentrations. In this thesis, only the applicable portions of the curves are used in the form «of straight line approximations as will be discussed later. The model is developed in four main steps as shown in figure 7: (a) In section 2.1, the base analysis, an expression is derived for final collector-base junction depth, X. , as a function of base sheet resistance, r . . (b) In section 2.2, the emitter analysis, an expression is derived for emitter junction depth, X. , as a function of both emitter sheet resistance, r se , and emitter diffusion time, t . e - 16 - (c) In section 2.3, an expression is derived relating pinch sheet resistance, r , and base width, W . P ° (d) In section 2.4, pinch sheet resistance data is used to calculate W from which emitter push, X , is modelled. r o ep Note that in each section a different spatial design parameter is modelled as a function of a sheet resistance. 2.1 Base Analysis In this section an expression for X. derived. as a function of r . is To do this, each of the major steps in the formation of the base (boron predeposition, boron drive-in, and post boron oxidation) is analyzed in order to obtain results needed in the subsequent analysis. The logical development is shown in figure 8. The parameters in boxes are process variables which are set at specific values; those in triangles are measured sheet resistances; those in circles are calculated values. Equations used to calculate the encircled parameters are shown in brackets. The four main steps, each discussed in a separate section are separated by dotted lines. the one prior to it. Each analysis builds on the results of Thus, the predeposition analysis (section 2.1.1), results in a calculated value for the total number of impurity atoms deposited, Q , and an equation for diffusion constant, D, as a function of diffusion temperatures, T. These then become the inputs to the drive-in analysis (section 2.1.2). Measurements used in this analysis are control wafer data from 100 diffusion lots shown as distributions in figure 9. - 17 - Detailed calcula- tions are presented in Appendix I. conditions investigated development. is Only one of the two predeposition presented as an example for the model However, both conditions are used, for example, to derive the D vs. T expression shown as equation (8) and to give added verification of the results at other points in the development. 2.1.1 Boron Predeposition The objective of the analysis in this section as shown in figure 8 is to obtain a value for Q and an expression for D as a function of T. The predeposition of Boron is accomplished by bubbling nitrogen through boron tribromide continuously during the heat cycle. This guarantees an ERFC profile and a constant surface concentration, N , the level of which is determined by the solid solubility of Boron in silicon at the predeposition temperature, T . This allows us to use the extrapolation of the boron solid solubility curve shown in figure 10. Hence, the surface concentration is calculated from: In N sp = (9.17 x 10~4)'T Next, real data is introduced. p + 46.54 (5) The mean of the predeposition base sheet resistance r , (figure 9) and the value of N just calculated sp sp are substituted into an approximation of the applicable portion of the pertinent Irvin curve to calculate a predeposition junction depth, X. . The approximation, as shown in figure 11, is given by: In N sp = 1.14 In (1/X. • r ) + 40 jp sp 18 (6) At this point, the diffusion constant, D , is evaluated by using an approximation to the ERFC curve as shown in figure 12. The resulting expression is: ln (N bc/Nsp) =6.24-5.59 <XJp/2 yTD^) The value of the background concentration, resistivity of the epitaxial layer. N. The nominal material used in this Investigation is 1/2 ohm-cm. (7) is gotten from the resistivity for the According to Irvln's curve for resistivity versus concentration [20], 1/2 ohm-cm is equivalent to a concentration, N. is given, X. and N = 10 cm" . The diffusion temperature, T , were calculated previously; thus, we have values for four variables (N. be , t , X. , and N p jp sp ) which are substituted into equation (7) to produce a value for the diffusion constant at 875°C. i Repeating the calculation for the other predepositlon condition results in a second value of D . The two sets of vpoints: (T = 875°C, P P 5 5 D = 1.31 x 10" ) and (T = 870°C, D = 1.17 x 10" ) are used to generate the equation: ln D = .023T - 54.39 (8) Equation (8) is used in the next analysis to determine the diffusion constant at drive-in temperature, D.. In doing so, a coherent transi- tion from one part of the analysis to the next is provided. In addi- tion, a plot of equation (8) as shown in figure 13 compares favorably with similar data from the literature. work lends credibility to this analysis. 19 - The good agreement with other's Finally, the expression for an ERFC profile: ■ Q p = 2N sp v/FT/TT V ' " p (9) p is used along with the diffusion time, t , and the calculated values for N and D' to calculate the total number of impurities, Q , introduced into the silicon during the predeposition cycle. In this analysis of the predeposition cycle a value of Q was calculated and an expression for D as a function of T (equation [8]) was derived. These two results are now used in the analysis of the base drive-in cycle. 2.1.2 Base Drive-In For both predeposition conditions the drive-in was done for 88 minutes at a temperature of 1100°C. Equation (8) is used to calculate the drive-in diffusion constant, D., for T. = 1100°C. During the drive-in cycle no additional impurities are introduced; the predeposition provides a finite source, hence, a Gaussian profile is assumed. In addition, if segregation coefficient effects are ignored, the number of impurities after drive-in, Q., equals the number predeposited, Q , i.e. Qp = Qd Now the value of Q (10) calculated in the previous section, along with the calculated value of D. and the drive-in diffusion time, t., are substituted into the equation for total impurities under a Gaussian profile: 9d = N sd/WT - 20 (11) in order to calculate the surface concentration at the end of the drivein cycle, N .. Next, an approximation for the Gaussian curve as shown in figure 14 as given by: In (Nbc/Nsd) =6.25 -• 2.05 (Xjd/2 ^D^) (12) along with previously determined values for N. , N ., D., and t. is used to calculate the base-collector junction depth after drive-in, X. .. Thus, in this section, values have been calculated for both N . and X.., two parameters together which characterize an impurity profile. These results can now be used 1n the post boron oxidation analysis. But before proceeding, the accuracy of this analysis can be checked by using the approximation to the pertinent Irvin curve shown in figure 15 as given by: In N . = 1.32 In (1/r .• X. .) - 39.1 sd sd jd (13) and the values for N . and X. . to calculate the base sheet resistance after dr1ve-1n, r ., and comparing the result to the measured values. For both predepositlon conditions the values calculated in Appendix I for r . match the measured values, i.e., the mean of the r , distribution shown 1n figure 9. Condition A B Calculated r sd. 137 126 21 Measured r sd. Units 136 126 ohms/square ohms/square 2.1.3 Post Boron Oxidation o In order to provide an emitter diffusion mask a nominal 5000A of oxide is grown in the base region by subjecting the wafers to a 900°C steam ambient for 210 minutes. The silicon atoms depleted from the surface by the formation of the silicon oxide amount to a thickness, X , which 1s 45* of the oxide thickness, X : for an oxide thickness of 5000A: X OS = .45 ft The effect this removal ox ) = .225 x 10~4cm (14) of silicon at the surface has on the sheet resistance is evaluated by Introducing the (X/XJ Irvin curves as defined 1n figure 16. parameter from the Again a straight line approxi- mation as shown in figure 15 is used to produce the expression: In N . = 1.32 In [1/r ..(X. . - X )] - 2.27(Xnc/X, J + 39.1 sd sb jd os os jd (15) Using values previously determined for N ., X.., and the mean value of X , a value of r . 1s calculated using equation (15). r . 1s the final os sb sb base sheet resistance. As shown in Appendix I, values can be calculated for both predeposition conditions: Condition Calculated r . A B 193 176 Measured r ■ 193 174 Units ohms/square ohms/square Since the final base-collector junction depth, X. , is defined by: jc jc jd os equation (15) provides a means for calculating r . values as a function of Xjc. - 22 ^ X. But, before this Is done, the dependence of r . on X and hence on is evaluated by investigating the spread in the X distribution (figure 9A) to see if it corresponds to the spread in r . . o Taking the X OX range to be 4000-6000A, the corresponding values of X along with the values for N . and X.. from above, are substituted os sd jd into equation (15) to calculate values of r .. Sample calculations are presented in Appendix I. The results are shown below: Parameter Condition A Condition B Xox Xos calc. r . meas. r*. 4000 .18 180 177 4000 .18 165 155 Units o 6000 .27 207 209 A microns ohms/square ohras/square 6000 .27 189 193 These results suggest that for a given set of conditions the variation in base sheet resistance is adequately explained by the variation in X which now provides the means for modelling the r . as a function of X.. 2.1.4 The Base Diffusion Model The good agreement between calculated and measured values at three points in the process1 for two predeposition conditions supports the correctness of the analysis, which is interpreted as follows: (a) The impurity profile as defined by the surface concentration and the junction depth is essentially constant after both predeposition and drive-in for a given set of conditions. (b) The variation in the base sheet resistance is mainly due to the depletion of silicon at the surface during oxidation. 23 the post boron The distributions presented in figure 9, show that substantial variation occurs prior to the post-boron oxidation. This, no doubt, is due to variations in junction depths and surface concentrations at both predeposition and drive-^n. Nevertheless, the four parameters involved, N , X. , N ., and X.. are assumed constant for a given set of conditions, jp sd jd First of all, it was demonstrated in section 2.1.3. that virtually all of the final base sheet resistance variation is attributable to the variation of X. vary ^ery little. through the X parameter, consequently N Secondly, any variation in X, for as a part of the total variation in X. . and N . and X. . 1s accounted Hence the assumptions are valid. At this completed. point, the base diffusion part of the model can be As shown in Appendix I, equations (15) and (16) can be used with the constant values for X.. and N . calculated in the previous section to calculate a series of values of r . for incremental values of X . The results are plotted in figure 17, A linear regression line through the calculated points results in the following expression: = ^.38 - (4.18 x 10"3).rsb X. Thus, we have derived an expression for X. proceed to the emitter analysis. A " 24 - in terms of r . (16) and now 2.2 Emitter Diffusion Analysis The objective is to derive an expression for the emitter junction depth, X. , as a function of the emitter diffusion time, t , and the emitter sheet resistance r . The emitter is diffused by bubbling nitrogen through phosphorous tribromide for a sufficient part of the heat cycle to guarantee that a continuous supplied at the silicon surface. at 950°C. source of impurities is The diffusion temperature, T , was set The diffusion time, t , is varied from run to run on the basis of the base sheet resistance of the wafers 1n the lot 1n order to produce the desired pinch sheet resistance, r . Because the model is restricted to a particular set of conditions, the anomalous impurity profile usually observed for phosphorus [21] is ignored and an ERFC profile is assumed. This allows the use of the pertinent Irvin curve in determining the emitter junction depth, X. , from control wafer sheet resistance, r se , measurements. Since not all of the phosphorous impurities are electrically active [13], the surface concentration is taken from Lee's curves instead of assuming that it is equal to the solid solubility of phosphorus in silicon at 950°C. Never- theless, the continuous source condition does guarantee a constant sur20 -3 face concentration, N , which is taken (from Lee) to be 6 x 10 cm . se If we assume neglible oxidation (the diffusion is done in a non-oxidizing atmosphere) such that X = 0, then the pertinent Irvin curve for X/X. = 0 can be approximated, as shown in figure 18, by the following: In Nse = 3.5 In (l/r^X^) + 23.8 25 (17) Since at 950°C, N = 6 x 10 1 r / 20 cm -3 oXio , equation (17) can be rewritten as: = 962 (ohms)"1 (18) i At this point, the relationship between the emitter sheet resistance and the emitter diffusion time is developed empirically. Measurements of r on control se wafers were made diffusion lots run for various diffusion times. plotted in figure 19. for a number of The resulting data 1s To allow analytic calculations, the data was fit with the following expression: r se where t = 68/ V^e~ fohn>s/square) 1s measured in minutes. d-9) To find the relationship between X. and t , equations (18) and (19) are solved simultaneously to eliminate r se : Xje = AS3\ft^ (20) where t is again in minutes and X. now is in microns, noting that 3 e je previously all depths were in centimeters. The straight forward analysis in this section has produced expressions which allow calculation of X. from either sheet resistance data (eq. 18) or from emitter diffusion times (eq. 20). 2.3 Pinch Sheet Resistance The sheet resistance of the pinch resistor (figure 6), r , has a strong relationship with both the gain, h- , and the saturation current, I , of the transistor element. For this reason, it 1s commonly used in the industry as a primary control parameter for diffusion processes. this section, pinch sheet resistance Is tied - 26 into the In rest of the diffusion model by deriving an expression for r vertical base width, W . as a function of the Assuming that the emitter diffusion forms a step junction, the sheet resistance of the base layer, i.e., the pinch sheet resistance, 1s associated with portion of the boron base profile not converted by the emitter diffusion. This shifts the Irvin curve to the X/Xj = .8 range as shown 1n figure 20. The approximation can be expressed as follows: In N . » 3.6 In (1/r-W ) + 25 [(X. sd p o jp - W )/X. .] + 22.35 o jd (21) For a given set of conditions, N . and X. . are constant, so substitution of incremental values of W Into equation (21) generates a set of values for r , as presented in Appendix II. The results are plotted in figure 21 and the points are fit by the following equation: In W = 2.5 - .357-ln r o p Referring to figure 16 we see that: o ■ W x jc - x je where X + x 1s the amount of emitter push. ep now be used to evaluate X . ep 2.4 ep (22) (23 » Equations (22) and (23) can Emitter Push Analysis In a production environment, a direct measurement of emitter push by the angle lap and stain method 1s impractical. not used in this investigation. Consequently, it was Instead, values for emitter push, X were extracted from pinch sheet resistance data. using an existing diffusion model. 27 - , The data was generated ^ In r = P. - 2.8-ln W f o = 8.55 - .005-rb Pf (24) p (25) W'o = .5 + .15 \/230 - r'b '- "■" .15 \/t - 40' v •*' •*" v "u "e This 1s an empirical model match the measured values. (26) for which calculated values Of r closely P But it can't be coupled with the transistor model which Is developed in Section 3 because the emitter push effect 1s contained in the empirically determined push factor, Pf, instead of 1n the W term. Consequently, it does not provide a means for translating easily measured sheet resistance Into the base width terms, W which appear in the gain model. generating accurate r It does serve, however, as a means for data for ranges of r. and t . The logical development of the X cally in figure 22. and W, derivation is shown schemati- The procedure is as follows: (a) Calculate r using the empirical model defined by equations (24), (25), and (26) for incremental valyes of t and r. as in the example presented in Appendix III. (b) For each value of r. and t used in step (a) calculate a corresponding X. and X. using equations (16) and (20). (c) Using the r values from step (a) and equation (22) calculate values for W . o (d) For values of X. , X. , W use equation (23) to calculate X jc je o ep for each combination of t and r. . e b The detailed calculations are presented in Appendix III. both conditions are plotted in figure 23. following expressions: 28 Values for Curve fitting yields the Xep=mte+I (27) m = (2.5 x 10"5)-r. - .00.34 (28) I = 1.19 - .0058-r. +k (29) b D where k is a coupling parameter which links the two predeposition conditions by their respective diffusion lengths as follows: k = .13-(106 x L ) - .22 L P ■ (30) (31) V/VP Equations (27) through (31) allows us to calculate values for emitter push using the easily measured parameters r. , t , and L , thus eliminating the need to angle lap. The technique developed in this section which allows us to calculate emitter push can be supported in two ways. First, the equations are in accordance with the observations in the literature [7]. For example, equation (27) shows that X time and equation (28) shows X junction depth, X. . increases with emitter diffusion ep increases with decreasing basecollector Equations (29) and (30) imply that X increases with greater base doping (base surface concentration). Secondly, the enhancement factor, E , calculated using the approximation given by Jones and Willoughby [8]. X4„2/(t. + t ) = (X. + XoJ2/(t. + E t ) jc b e jc ep b p e where t is the equivalent base diffusion time done at the emitter temperature, can be plotted as shown in figure 24. X ep and E (32) p As can be seen, both are within reasonable range of other's results if differences of experimental conditions are considered. 29 3.0 TRANSISTOR MODEL Device models such as Ebers-Moll or Gummel-Poon are useful for describing transistor action over a wide range of operating conditions. This is essential for circuit analysis. Hence, the EM and GP models characterize current, frequency, and temperature behavior of the transistor. Once a device has been designed and proven-1n, its per- formance Is ensured by measuring it against a test specification. digital For bipolar integrated circuits, the tests are made at specific operating conditions. It is not common practice, for example, to test device performance at various levels of current, frequency, and temperature., Rather, the assumption Is made that reprodudbility of the design parameters afforded by controlled processing guarantees operation over a wide range of conditions. Therefore, the model designed as an aid to yield improvement can be based on the assumption that many of the variables are constant while others vary only within a narrow range. Considerable simplification of the transistor theory can be made at the expense of generality without affecting the accuracy of the results, in fact, Improving it. 3.1 Gain Analysis Chin [1] observed that when the emitter diffusion "pushed-through" the original collector-base junction, i.e., when: X. > X. . (see figure 2) (33) je jd a large shift in gain was observed. He explained this by postulating two components for the base width as shown 1n figure 2. - 30 - Furthermore, he argued that gain depends on W X. > X. .. when X. < X.. and it depends on W. when This discontinuity can be dealt with more analytically by explaining the phenomenon in a different way. If instead of considering the transistor action to occur locally either at W or at W. depending on the device geometry, we assumed that the base current splits in two (bifurcates) no matter what the geometry, then the transistor can be represented by the equivalent circuit shown in figure 25. The config- uration is similar to a T-shaped emitter device [22]. Because of. the proximity of the collector in the region of W,, part of the base current, I.., will flow through the lateral base width at the periphery of the emitter junction and part, I. the normal vertical base. will flow through In short, the device acts like two transis- tors in tandem and the collector current will also have two components, I , and I cl CO . Now the component form of the currents can be substituted into the definition of the grounded emitter current gain: (34) "ft-V'b to give: h fe - "cl + 'co'/Obl + 'bo' (35 > Rearranging, we can write: : + h. = W^l <Vcl> x ! bo* !co (36) "^T We now define the gain for the "local" transistors: B o " V'bo (3?) Bi = W^i (38) 31 Substituting (37) and (38) into (36) gives: h^ = Since in the "Chin 1 * ^o ^ effect" *cl when (39) the emitter "pushes-through" the original base, the transistor acts as though the base width is W., we can draw a similar conclusion 1n the case of the bifurcation effect. Namely, negllble. when W. gets l small, W o is "p1nched-off" and <» I becomes CO This can be stated analytically by the following condition: I™ "- 0 CO as w,—-0 1 10 CO Cl from which 1t may be deduced that: W1,! = ,40 Vo > Assuming that the following approximations can be made: 1/B. = C.-W.2 and 1/B 111 where C, and C ' = C *W} (41) 000 are constants of proportionality, substitution of (40) and (41) into (39) results in the following: hfe = (W0 + where C> and C, oi empirically to be: are 2 Wl)/(CiWl + CoWlWo) (42) arbitrary constants which were determined C, = .063 and C = -.007 1 o Equation (42) 1s the gain model. This model applies to a specific device made using a fixed set of processing conditions. Its value 1sS found 1n analysis of data for the purpose of optimizing variables to Improve yields. In addition, it is also which useful for explaining certain observations Increased understanding of Integrated circuit manufacture. - 32 - lead to an To test the model, h.. data was gathered for a number of wafers by measuring, the gain of the transistor element on the special test site on each wafer. Associated with each wafer there is also an emitter diffu- sion time, t , a,nd a base sheet resistance, r. from which W calculated. and W. were The procedure is shown schematically in figure 26; details of the calculations are presented in Appendix IV. serve to illustrate how the model is used. (a) calculate X. The calculations also For each wafer: from r. and equation (16) (b) calculate X.jc from te and equation (20) (c) calculate X from te, r. and equations (27), (28), and (29) (d) calculate W from X. , X. , X and equation (23) o jc je ep ^ (e) calculate W, from the following: M (43 l - Xjc - "je ' To ensure that the analysis is on target, the calculated value of W can be used in equation (22) to calculate pinch sheet resistance which can be compared to the measured value of r for each wafer. P Calculations were made for a number of wafers from which those with W ~ .5um were selected and their corresponding measured values of h^ plotted against the corresponding calculated values of W.. The data is plotted in figure 27 along with the theoretical curve generated using equation (42) for W = .5um. The sharply rising curve explains the high gain values which are not explained by other gain models, thus providing evidence for the bifurcation effect. Since all of the data points have approximately the same value of W , hence the same r , 1t is apparent that W, is a better determinant of gain than 1s the currently accepted - 33 - gain control parameter, r . related to the Furthermore, since W and W. have been sheet resistances and the process variables by the diffusion model, a complete analysis of transistor gain can be done. Process variables such as predeposition diffusion length can be analyzed and adjusted to produce a desired gain for a given W . In the same way, the gain to pinch sheet ratio can be determined by controlling the amount of emitter push. The gain to pinch ratio 1s a figure of merit commonly used 1n I.e. analysis since it relates to the speed of the device. Thus, a comprehensive model has been derived which extends from device characteristics, h- , to the pertinent process variables. At this point, it should be noted that the primary inputs to the model are in-process measurements, r , r, , r or L . or process variables, t In. the manufacturing environment it 1s often necessary to do the data analysis with CATS measurements since the in-process measurements are not always readily available. must relate the in-process r Therefore, to complete the model, we measurements r.trtr b e p to their corresponding CATS measurements R., R , R . 4.0 SHEET RESISTANCE C00RELATI0NS Unfortunately the values for the sheet resistances measured at CATS are not the same as those measured in-process. good corelation. Fortunately there is The coupling of the diffusion model to the transistor model is finalized by defining these corelatlons. 34 4.1 Emitter Sheet Resistance Figure 28 shows an in-process emitter sheet resistance, r made on control wafers plotted agairi'st the same measurement made at CATS, R . The increase in sheet resistance is a straightforward linear relationship given by: Re = rse The shift is a real + 4.8 (44) change in sheet resistance resulting from the depletion of silicon from the surface at the post emitter oxidation. 4.2 Base Sheet Resistance As shown in figure 29, there is a greater spread in the plot of l?ase sheet resistances made at the in-process vs. CATS operations. reason for this is twofold; subsequent processing, Base sheet resistance and 1ST The (1) base sheet resistance is affected by (2) two methods of measurement are used. measured in-process on each wafer prior to the emitter diffusion and there is some movement of the base junction during the emitter diffusion and subsequent processing. creases and one would expect r. But since X. in- to decrease, the net Increase in r^ between the in-process measurement can be attributed to the differences in measurement techniques.- In-process, r. is measured on a "sea horse" pattern, essentially a rectangle as shown in figure 6. The measurement is a function of geometry, hence, depends to some extent on line width control and side diffusion. Hence, the variation is greater than with a van der Paaw measurement [23] which is Independent of geometry. In fact, a van der Paaw measurement made at the same point in-process as - 35 - the sea horse 1s typically 30 ohms/square higher. , Subsequent processing reduces the sheet resistance so that the van der Paaw measured at CATS 1s a net of 22 ohms/square higher on the average and the corelation can be written: R b 4.3 = r b + 22 (45) Pinch Sheet Resistance In figure 30, a plot of CATS pinch sheet resistance, R , against the corresponding in-process pinch sheet, r , shows more scatter than does the base sheet curve. Since there are no high temperature oper- ations after the emitter diffusion, the change in pinch sheet from inprocess to CATS can not be attributed to any movement in the junctions; consequently, the shift in r is attributed to the method of measure- ment. In process, the p1nch-res1stor is not metallized, therefore, as shown 1n figure 31, a Kelvin contact 1s utilized. emitter region 1s allowed to "float". p1nch-res1stor 1s metallized In this method, the At CATS, on the other hand, the and a Kelvin contact is not possible. Instead, the emitter 1s tied to one end of the base region as shown 1n figure 31. A constant current is forced through the base and a voltage measured to allow a calculation of resistance. emitter causes a depletion layer spread. The potential on the If W. 1s small, the depletion layer spread "p1nches-off" the base causing an effective Increase 1n resistance and leads to anomalously high CATS R measurements. p is a function of W, which can be expressed by: R = (.35 - .5w.) r 2 P 1 P - 36 - Thus, R„ P (46) 5.0 DISCUSSION t> The three corelation formulae, equations (44), (45), and (46) align the diffusion model to the transistor model and allow in depth analysis of the various factors affecting the gain of the transistor. The equa- tions which make up the model are listed in Appendix V for convenience. Gain is only one of the Important characteristics of a bipolar transistor; two others are speed and junction breakdown voltage. Although an intensive treatment is beyond the scope of this paper, a conjectural discussion of speed and voltage breakdown relating these characteristics to the results of this investigation is now presented. 5.1 Speed Characteristics The basic bipolar transistor is used in an integrated circuit both as an amplifier and as a switch. As an amplifier operation over a range of frequencies is important; as a switch, the speed of switching is important. In both cases, frequency characteristics and switching speed, there is a strong dependence on the base width. In light of what has been discussed previously, it is of interest to ask - which base width? Although no direct speed or frequency measurements were made in this investigation, there is indirect evidence that W. important role. plays an It has been observed that for devices which include parametric tests at high frequency, yields increase as the gain to pinch sheet resistance ratio, h/r, increases. 37 h/r can be related to W. represents a constant W constant r . calculated. practice. of VI,, will = ,.5um which from equation (22) Using the h* .5 and a constant r by considering figure 27. The curve implies a range of the curve for W, values from .2 to = 7600 ohms/square, an h/r range from 13 to 50 is This range of h/r is greater than normally observed in But, remember an r result in an R P = 7600 measured in-process, for a range A at CATS which ranges in accordance with coorelation formula, equation (46), from 8000 to 14000. (46) to translate r the curve shown to R Using equation and plotting the corresponding h/r versus VL, in figure 32 was generated. As shown, h/r varies according to W. from 15 to 35, a range typically observed for the subject transistor. Hence, the model explains this important h/r parameter and leads to greater understanding of the speed characteristics of a bipolar transistor. We can now conclude that speed increases as W. decreases. The model can be used to control W. and improve the speed characteristics of the device. 5.2 Voltage Breakdown Characteristics The collector-base junction depletion layer spreads into the base region as the applied voltage increases. If W the emitter depletion layer is halted at the is narrow, the spread in junction, the field increases rapidly, and avalanche breakdown occurs at a lower voltage than it would had there been no emitter. This is the well-known "punch-through" condition described by: BV ces( = BV . - BV . = V. cbo ebo pt - 38 - (47) where BV-ces Is the collector to base breakdown voltage with the emitter J shorted dto the base, BV . 1s the collector to base breakdown voltage with the emitter open, BV . ,1s the emitter to base breakdown voltage. Since the onset of the $ . condition depends on the width of the base, it is important to evaluate the impact of W.. [1] data, BV . was plotted versus gain as shown in figure 33. curve shows a strong degradation of BV . devices. Borrowing Chin's The for high gain, hence low W. This effect would preclude the control of W. as a viable means of increasing the speed of the device were 1t not for the second ^ observation also plotted 1n figure 33. v 3 BV 1s the breakdown of the ceo device when the voltage is applied from emitter to collector with the base open as given by any standard text on device characteristics as: ■ceo ceo " "'cboV^Ve c where n is a technology dependent constant. does not show the degradation that BV . theory 1n that the BV . (infinite) junction. impact on BV 1n (48) As figure 33 shows, BV does. equation (48) This merely confirms the is that for a planar Therefore, emitter push does not have the same that it has on BV . normally biased circuit, , 1s since BV This 1s important since in a BV_ which determines the minimum ceo acceptable value usually around 8 volts. Consequently, 1n spite of the degradation of BV . it . is relatively unaffected, it is possible to maximize the speed by controlling W. and still produce a device with useable voltage breakdown characteristics. 39 5.3 Summary By specific restricting set of the model to a particular device made using a processing variables, developed which allowed an a extension characteristics to process variables. simplified methodology was of the model from device This allows a more direct and in-depth analysis of all the factors Involved in the gain of the device. Using the simplified methodology, a diffusion model was developed providing a means to control the diffusion process, I.e., given a base sheet resistance measurement on a wafer an emitter diffusion time can be determined to produce any desired pinch sheet resistance. the diffusion model also provides a means for In addition, translating easily measured sheet resistances, r.be , r , and r p into difficult to measure spatial design parameters, X. , X. , W , and W,. Since this eliminates the need for angle lapping and staining as a measurement technique, W and W. can be included in routine data analysis. The ability to calculate W and W. is important since it was shown that the gain of the device depends on the bifurcation effect. Emitter push results in a perturbation of the collector-base junction which configures the base width into two spatially distinct components, W W,. As a result, the base current bifurcates. and This effect was used to derive the transistor model, an expression for gain as a function of W and W.. The transistor model is coupled with the diffusion model through three coorelation formulae which relate measurements of sheet resistance made in-process to measurements made at CATS. - 40 The result is an effective, practical model which allows in-depth analysis leading to an increase in the understanding of bipolar junction integrated circuits. - 41 - References [I] R. J. Chin, "Characterization of the Anomalous Diffusion Effect: Emitter Push-Out for a N-P-N Transistor", Master's Thesis, Lehigh University (1982). [2] T. E. Idleman, F. S. Jenkins, W. J. McCalla, and D. 0. Pederson, "SLIC - A Simulator for Linear Integrated Circuits", IEEE. J. Sol. St. Crts., SC-6, pp. 188, (1971). [3] L. W. Nagel and D. 0. Pederson, "Simulation Program with Integrated Circuit Emphasis (SPICE)", 16th Midwest Symposium on Circuit Theory, Waterloo, Ontario, (1973). [4] J. J. Ebers and J. L. Moll, "Large Signal Behavior of Junction Transistors", Proc. IRE, v. 42, pp. 1761, (1954). [5] H. K. Gumrnel and H. C. Poon, "An Integral Charge Control Model of Bipolar Transistors", Bell Sys. Tech. J., v. 49, pp. 827, (1970). [6] D. A. Antoniadis and R. W. Dutton, "Models for Computer Simulation of Complete I.C. Fabrication Processes", IEEE. J. Sol. St. Crt., SC14, pp. 412, (1979). [7] A. F. W. Willoughby in "Impurity Doping Processes in Silicon", F. F. W. Wang, editor, North Holland, N.Y., (1981). [8] C. L. Jones and A. F. W. Willoughby, "Studies of the Push-Out Effect in Silicon", J. Electrochem. Soc, v. 122, pp. 1531, (1975). [9] K. Tamiguchi, K. Kurosawa, and M. Kashiwagi, "Oxidation Enhanced Diffusion of Boron and Phosphorus in (100) Silicon", J. Electrochem. Soc, v. 127, pp. 2243, (1980). [10] A. M. Lin, D. A. Antoniadis, and R. W. Dutton, "The Oxidation Rate Dependence of Oxidation - Enhanced Diffusion of Boron and Phosphorus in Silicon", J. Electrochem. Soc, v. 128, pp. 1131, (1981). [II] S. Mizuo and H. Higuchi, "Anomalous Diffusion of Boron and Phosphorus in Silicon Directly Masked with Si^N., "Jap. J. Appl. J 4 Phys., v. 21, pp. 281, (1982). [12] K. Tsukanoto, Y. Akasaka, Y. Watarl, Y. Kusano, Y. Hlrose, and G. Nakamura, "Arsenic - Implanted Emitter and Its Application to VHF Power Transistors", Jap. J. Appl. Phys. v. 17, pp. 187, (1978). ^ - 42 - [13] D. B. Lee, Phillips Res. Suppl. No. 5, (1974). [14] S. M. Hu and T. H. Yen, "Approximate Theory of Emitter Push", J. Appl. Phys., v. 40, pp. 4615, (1969). [15] S.^ Ward and T. I. Prltchard, "Characterization of the BaseD1ffusiv1ty Enhancement Factor 1n a Phosphorous-Emitter, BoronBase Transistor Structure", v. 16, pp. 253, (1982). [16] D. Lecrosnler, M. Gauneau, J. Paugam, G. Pelous, F. Rlchow, "LongRange Enhancement of Boron D1ffus1v1ty Induced by a H1gh-SurfaceConcentration Phosphorous Diffusion", Appl. Phys. Lett., v. 34, pp. 224, (1979). [17] Y. Ishlkawa, Y. Saklna, H. Tanaka, S. Matsumoto, T. Num1, "The Enhanced Diffusion of Arsenic and Phosphorus 1n Silicon by Thermal Oxidation", J. Electrochem. Soc, v. 129, pp. 644, (1982). [18] S. M. Hu, P. Fahey, R. W. Dutton, " On Models of Phosphorous Diffusion 1n Silicon", J. Appl. Phys., v. 54, pp. 6912, (1983). [19] R. B. Fair and J. C. C. Tsa1, "A Quantitative Model for the Diffusion of Phosphorus 1n Silicon and the Emitter Dip Effect", J. Electrochem. Soc, v. 124, pp. 1107, (1977). [20] J. C. Irvln, "Resistivity of Bulk Silicon and Diffused Layers 1n Silicon", Bell Sys. Tech. J., v. 41, pp. 387, (1962). [21] R. B. Fair 1n "Impurity Doping Processes in Silicon", F. F. W. Wang, ed., North Holland, N.Y. (1981). [22] N. D. Jankovlc, "T-Emitter Bipolar Power Transistor with Negative-Temperature-Gradlent Current Gain", Electronics Letter, v. 18, pp. 1085, (1982). [23] L. J. van der Paaw, "A Method of Measuring Specific Resistivity and Hall Effect of Discs of Arbitrary Shape", Phillips Res. Dev. v. 13, no. 1, (1958). 43 - Appendix I - Base Analysis Calculations 1. For T = 875°C, calculate N In N sp = (9.17 x 10"4) T from equation (5) + 46.54 p In Ncn = 47.34 sp N 2. For r sp 20 -3 = 3.63 x l<ruciii- = 148 ohms/square, N from step 1 calculate X. in Nsp = 1.14-ln (lAJpTsp) + from (6) 40 In (3.63 x 1020) = 1.14-ln (1/148-X.J + 40 = 1.14 x 10"5cm X. 3. For t P = 46 x 60 = 2760 sec, N. = 1016cm~3, N from step 1, X, DC ' Sp JP from step 2, calculate D from (7) P in (Nbc/Nsp) =6.24 - 5.59 (Xjp/2 V^Tp) In (1016/3.63 x 1020) = 6.24 - 5.59'(1.14 x 10"5/2 \/2760-D ) = 1.31 x 10'5(cm2/sec.) D 4. For N sp from (9) Q p " 5. from stepK 1, D P from step 3, t P = 2760 sec. calculate Q 2 N sp\/Vp"/1T Q = 2 (3.63 x 1020)-\/(1.31 x 10"5)- (2760)/TT Q = 2.44 x 1015cm'2 For Td = U00°C, calculate Dd from (8) In Dd = .023Td - 54.39 InD, = .023 (1100) - 54.39 d Dd = 2.32 x 10"13 (cm2/sec.) - 44 - P Appendix I: 6. Base Analysis Calculations - (Cont'd). For Qd = Q 15-2 °& = 2.44 x 101 cm , td = 88 x 60 = 5280 sec, and -Dd from step 5, calculate N . from (11) = N Qd sd'\/ -^Vd 2.44 x 1015 = N$d (2.32 x 10"13)(5280) Nsd = 1.33 x 1019cm"3 7. = 1016cnf3, t. - 5280 sec, D. from step 5, N . from step 6, For N. calculate X-d from (12) In (Nbc/Nsd) = 6.25 - 2.05 (XJ(j/2 x/D^) . In (1016/1.33 x 1019) = 6.25 - 2.05 (X../2 \/(2.32 x 10~13)(5280) Xjd = 1.865 x 10"4cm 8. For N d from step 6 and Y... from step 7, calculate r . from (13) In N . = 1.32'ln (1/r . X. .) + 39.1 sd sd jd 19 In (1.33 x 10 ) = 1.32-ln (l/[r d]-[1.865 x 10"4]) + 39.1 r . = 126 ohms/square 9. For X = .225 x 10 -4 cm, N "» d from step 6, and X.rf from step 7, calculate r . from (15) SD In N . = 1.32-ln [1/r /(X. . - X )] - 2.27-(X /X J + 39.1 sd sb jd os os jet In (1.33 x 1019) = 1.32-ln [1/(1.865 - .225)-10~4rsb] - 2.27-(.225/1.865)-10~4 + 39.1 r . = 176 ohms/square 45 - Appendix II - Calculation of R vs. WQ From equation (21) 1n the text In N . = 3.6-ln (1/r W ) + 25-[(X.,-Wj/X ..] + 22.35 sd p o jd o jd and N . = 1. 33 x 1019, X, . = 1.865 x 10"4 sd Jd of W0 : Ho .2 .3 .4 .5 .6 .7 .8 .9 ( W/Xjd substitute Incremental values 1 59,700 27,400 14,100 7,810 4,470 2,650 1,600 970 .893 .839 .785 .732 .678 .625 .571 .517 - 46 ohms/sq. ohms/sq. ohms/sq. ohms/sq. ohms/sq. ohms/sq. ohms/sq. ohms/sq. Appendix III - Emitter Push Calculations Sample calculation for rfe = 170 ohms/sq., t (a) = 90 m1n, From equation (25), rfe = 170, calculate Pf Pf = 8.55 - .005 r. Pf = 7.7 (b) From equation (26), r. = 170, t be = 90, calculate Wo WQ = .5 + .15 \/230-rb - .15 \/ te~40 WQ = .5 + .15 \J230-170 - .15 \/ 90-40 Irf (c) = .60 urn o From equation (24), P In r In r r (d) p T = 7.7, \in = .6, calculate r 0 p = P. - 2.8-ln W f o = 7.7 - 2.8-ln.6 = 9100 ohms/sq. From equation (16), r.u = 170, calculate X. jc Xjc = 2.38 - (.0042)rb XJc = 2.38 - (.0042K170) X. (e) = 1.65 urn From equation (20), t Xje - .153 X. (f) e = 90 min, calculate X, je te = 1.46 urn From equation (22), r D P from step (c), calculate W In Wn = 2.5 - .357-ln r o p In WQ = 2.5 - .357-ln (9100) W o = .47 urn - 47 0 Appendix III - Emitter Push Calculations - (Cont'd) (g) From equation (23), X.. from (d), X.Je from (e), W from (f), Ja calculate Xaep„ ° w0 = x jc " Xje + X<2P .47 = 1.65 - 1.46 + X >" ep .28 urn eat steps (a) through (g) for various values of r ± 170 170 170 190 190 190 3. t e 70 90 110 70 90 110 r x 4 P 4,800 9,100 17,700 6,800 14,300 31,900 1.68 1.68 1.68 1.59 1.59 1.59 Repeat for other predeposition condition A. - 48 je 1.29 1.46 1.61 1.29 1.46 1.61 V V W 0 .59 .47 .37 .52 .40 .30 X ap .20 .25 .30 .22 .27 .32 Appendix IV - Calculation of h1. ' Sample claculation for a wafer with t (a) For r. = 200, calculate X. = 63 min, r. = 200 ohms/sq. from equation (16) X. = 2.38 - .0042-r. jc b X. = 2.38 - (.0042H200) X._ = 1.54 urn (b) (c) For t For t = 63, calculate X.g from equation (20) X. = .153 \J~63 X. = 1.22 urn = 63, rb = 200, calculate X - for predeposition T L = 875°C, t from equation (27) to (31) = 46 min, per equation (31) = 1.9 x 10"6cm P and per equation (30) k = .027 and equation (29) can be rewritten as: I = 1.22 - .0058.rb I = 1.22 - .0058«(200) I = .06 - for r.b = 200, calculate m from equation (28) m = (2.5 x 10' 10"5).r. - .0034 b m = (2.5 x 10"5)«(200) - .0034 m = .0016 49 Appendix IV - Calculation of h- - (Cont'd) and equation (27) can be rewritten as: X = .0016*t + .06 ep e from which X can be calculated for t = 63 ep e X = (.0016)«(63) + .06 L ep = .16 (d) For X. from (a), X. from (b), X from, (c) use equation (23) jc je ep to calculate wQ W W W (e) For X. o o o = X, - X, + X jc je ep = 1.54 - 1.22 + .16 = .48 urn from (a), X. from (b), use equation (43) to calculate Ww = X - X l *jc \je Wr = 1.54 - 1.22 Wj = .32 urn (f) For W from (d) and W. from (e), use equation (42) to calculate .0 1 h fe hfe = (WQ + W^/LOeS Wx2 - .006 W^) h/ = (.48 + .32)/[.063'(.32)2 - .006-(.32)(.48)] fe hfe = 145 - 50 Appendix V - Model Equations 1. Base Diffusion X. = 2.366-k, rb k, = 2120 L + (1.6 x 10"4) 1 P 2. Emitter Diffusion Xje = .1535/^ \fte ■ 68/r e 3. Emitter Push Xon = mt + 1 ep e m = (2.5 x 10 -5, J ).r. - .0034 D k2 = 12,700-L 4. Pinch Sheet In r = 7.0 - 2.8.In W P 0 jc W, = X. 1 5. - .218 jc je o ep - X. je Gain fe .126-W,2 - .0186-W, Wrt 1 1 o 6. - CATS Corel ation R b R = r b + 22 +48 e R = (.35 - .5W.)-r 2 P 1 P e = r - 51 YIELDS COMPLIANCE CIRCUITS DIODES RESISTORS TRANSISTOR CIRCUIT CHARACTERIZATION DEVICE CHARACTERISTICS I—f~~l LEAKAGE RESISTANCE GAIN I CIRCUIT CHARACTERIZATION DESIGN PARAMETERS SURF. UNE WIDTH METAL PROC. P.R. PROC. PINCH RES. OPTIMIZATION PROCESS VARIABLES DIFF. PROC. I FIGURE. 1 CATEGORIZATION OF MODEL PARAMETERS -52- I EMITTER t_ —f m n-type EPITAXIAL SIUCON _J FIGURE 2. " BURIED LAYER \_ SCHEMATIC REPRESENTATION A BIPOLAR JUNCTION TRANSISTOR SHOWING THE EMITTER PUSH AND OTHER SPATIAL DESIGN PARAMETERS. -53- P TYPE SUBSTATE OXIDATION ATK PHOTO-RESIST ETCH OXIDE IMPLANT DIFFUSE OXIDATION PHOTO-RESIST ETCH OXIDE DEEP N+ DIFF.P fm[»ri>£m\*jjj/Fm[>j'jjIm\ ( P-SUBSTRATE T OXID..PR.ETCH BASE DIFF.B OXID..PR.ETCH EMITTER DIFF.P REMOVE OXIDE DEPOSIT EPI Si _____ L_ IHIIIIJ»H,IIIII .■■iiuiHiiLiiiiiHiTffiff N \P 1—M±J '-^tfrtjt^ttjtArifiE* / 1N» P-SUBSTRATE T OXIDATION PHOTO-RESIST ETCH OXIDE ISOLATION DIFF.B METALLIZATION i P-SUBSTRATE FIGURE 3. OUTLINE OF A STANDARD BURIED COLLECTOR PROCESS -54- |PH' CONCENTRATION 1 PAIR CONCENTRATION ELECTRON CONCENTRATION P+V'PAIR DISSOCIATION REGION P^V-—P+V+ e- DEPTH INTO SIUCON FIGURE 4. PHOSPHOROUS PROFILE SHOWING THE GENERATION OF VACANCIES ACCORDING TO THE FAIR-TSAI MODEL -55- BORON BASE PREDEPOSITION FIGURE 5. INTERELATIONSHIP OF THE DIFFUSION MODEL PARAMETERS -56- ■V, VAN DER PAAW PATTERN n c_r -AAAAAAAA-TD C L SEAHORSE PATTERN BASE DIFFUSED AREA EMITTER DIFFUSED AREA PINCH RESISTOR FIGURE 6. SHEET RESISTANCE PATTERNS ■57- INPUTS o I 1 " ' DIFF.TEMP. DIFF.TIME RESISTIVITYMEAS.SH.RES. ANALYSIS Tp* tpH Po* rsp- COMPARE D-f(T) WITH UT. BASE PREDEP. T VERIFICATION T QpCD=f(T)] •J- rl n 1 o £ l - -£- DIFF.TEMP DIFF.TIME RESISTIVITY BASE DRIVE-IN po ■ USE IRV1N TO CALCULATE r COMPARE TO DATA 7~ Nsd 2.1.3 . OX.THICK X^ POST-BORON OXIDATION, iXjc -1 2.1.4 USE IRVIN TO CALCULATE r COMPARE TO DATA r rsb 1- BASE DIFFUSION MODEL CXjc=f(rb)] 2.2 DIFF.TEMP. T„ DIFF.TIME t€MEAS.SH.RES. !>» — EMITTER DIFFUSION - C Xje=f(te)3 2.3 JUNC.DEPTH SURF.CONC. PINCH SHEET RESISTANCE — CWo=f(rp)] 2.4 PINCH SHEET rp — EMIT.DIFF.TIME tp-* BASE SH.RES. rfe— Xjd* Nsd" EMITTER PUSH CXep=f(rb.te)] FIGURE 7. LOGICAL DEVELOPMENT of the DIFFUSION MODEL -58- ^ 6> w i C73 ®- CIRV3—^ W CD rNpj ■C5D- > 2.1.1 <-. C9] (T)3 ...F. [^}-*C8]—K§) C 103 0-KDefJ—' © 2.1.2 ©■ -[ 1] =r:c 123 J Xjd>-^[13] 2.1.3 ©~—C 1 4]——W 2.1.4 -CXic=f(rb)]- FIGURE 8. LOGICAL DEVELOPMENT of the BASE ANALYSIS -59- CONDITION A 220 200 103 164 180 ohms sq. 160 140 136 120 CONDITION B PREOEf POST BORON .OXIDATION DRIVE-IN 190 170 ohms sq. 150 » 174 « w LjjUUlfy |UU snootm xa 130 KM X X 126 110 FIGURE 9. DISTRIBUTION OF CONTROL WAFER READINGS -60- OXIDE THICKNESS 7000 . » tm 6000 o A 5000 4000 FIGURE 9A. DISTRIBUTION OF MEASURED OXIDE THICKNESSES -61- 21 SOLID SOLUBILITY 10 0 _ 8 _ 7 6 - PUBLISHED CURVE 5 - 4 - (cm.) r4v lnS= (9.17X10 )*T+46.54 3 - 2 - 20 10 800 900 1000 _L X 1100 1200 DIFFUSION TEMPERATURE-T (C°) FIGURE 10. EXTRAPOLATION of the SOLID SOLUBILITY CURVE for BORON in SILICON -62- 10 21 X/Xj =.10 CONCENTRATION fi 10 20 t -3 (cm"° ) Y/ // 10 19 //I'lnN sp h = 1 •14-*(xjp*rsp)"i+40 / / / / / / // / / / / 10 16 Nbc = 10 p-type ERFC / / 18 - 1 20 ..._J . 50 i • i. ' 100 200 500 1000 CONDUCTIVITY-C rs (Xj -X)]"1 2000 C ohm-cm.]"1 FIGURE 11. APPROXIMATION for the IRVIN CURVE, p-type ERFC PROFILE -63- m -3 NORMALIZED CONCENTRATION ln(Nbc/Nsp)= 6.24-(5.59)(Xjp/2/iyt) 10 -4 L Nxx/'^s /H RANGE of INTEREST 10 10 -5 -6 Sfj i 2.6 i ' 2.8 » 3.0 ' ' 3.2 ' ' 3.4 NORMALIZED LENGTH- X/(2^Dt) FIGURE 12. APPROXIMATION for the ERFC CURVE -64- 10r«- DIFFUSION CONSTANT id13 lnD=.023*T-54.39 cm./i 10* COMPOSITE CURVE FROM THE LITERATURE (see REFC21] 10"5 v 10 lb K,i ' 900 ' ' 050 I 1000 I 1050 I L 1100 DIFFUSION TEMPERATURE-°C FIGURE 13. DIFFUSMTY of BORON In SILICON -65- 10 ■z NORMALIZED CONCENTRATION "n(Nbc /Ns) = 6.25-2.05(Xjd /{2^V6) -3 10 h RANGE of INTEREST Nbc/Ns -4 10 - GAUSSIAN- 1d5 J 2.2 1 I 2.4 L J 2.6 I 1 2.8 L 3.0 NORMALIZED LENGTH- Xjd /(2 \/Ddtd) FIGURE 14. APPROXIMATION for the GAUSSIAN CURVE 66- 10^o CONCENTRATION x/x-.J .2 .1 0 N cm. -1 = 1.32ln(rsd- Xjd) +39.1 ^t> Nbc = 10 type GAUSSIAN rl InNsd =1.32(rsb[Xjd-X0S]) -2.27()^/Xjd)+39.1 id" 10 20 50 100 CONDUCTIVITY- (XjC- fcb)~l 200 500 (ohm-cm.)"1 FIGURE 15. APPROXIMATION for the IRVIN CURVE p-type,GAUSSIAN PROFILE -67- 1000 CONCENTRATION -^ORIGINAL SILICON SURFACE SURFACE AFTER OXIDATION EMITTER DIFF. cm, hWrf><iiH - X os \jc J L -I .5 L J 1.0 i ' 1.5 DEPTH- (microns) FIGURE 16. SCHEMATIC REPRESENTATION of a DIFFUSION PROFILE -68- L 2.0 BASE SHEET RESISTANCE 200 _ 200 - 180 _ CONDITION A XJC =2.36-(3.79x10 )rsb r sb ohms sq. 160 - 140 - XJC =2.38-(4.18x10 )rsb CONDITION B 120 J I 1.4 1 I 1.6 I . I L 1.8 2.0 JUNCTION DEPTH- X.c (microns) FIGURE 17. CALCULATED VALUES OF BASE SHEET AS A FUNCTION OF THE BASE-COLLECTOR JUNCTION DEPTH -69- «& 0V CONCENTRATION -1 lnNse =3.5ln(rse • Xje) +23.8 NSd cm. 2 - 1020U .(6 Nbc=10' n-type ERFC 2 - 10 19 50 100 200 CONDUCTIVITY=(rse. xje) 500 1000 _L 2000 (ohm-cm>)"1 FIGURE 18. APPROXIMATION FOR THE IRVIN CURVE, n-type,ERFC PROFILE -70- EMITTER SHEET RESISTANCE DIFFUSION TIME-te(minutes) FIGURE 19. PLOT OF CONTROL WAFER EMITTER SHEET RESISTANCE vs. EMITTER DIFFUSION TIME ■71- CONCENTRATION x/x .8 CONDUCTIVITY= (rp W0 )~1 .7 (ohm-cm)"1 FIGURE 20. APPROXIMATION FOR THE IRVIN CURVE p-type,GAUSSIAN PROFILE ■72- 100 PINCH SHEET RESISTANCE BASE WIDTH- W0 (microns) FIGURE 21. PINCH SHEET RESISTANCE AS A FUNCTION OF BASE WIDTH -73- REPEAT FOR OTHER VALUES OF teirrb PLOT Xep CXep= f(te.rb)] FIGURE 22. LOGICAL DEVELOPMENT OF THE EMITTER PUSH DERIVATION -74- EMITTER PUSH A - .3 Xep - (um) _ INCREASING BASE SURFACE CONCENTRATION DECREASING COU£CTOR-BASE JUNCTION DEPTH CONDITION B .2 CONDITION A 40 60 80 100 EMITTER DIFFUSION TIME- te 120 (minutes) FIGURE 23. PLOT OF A CALCULATED VALUES OF EMITTER PUSH vs. EMITTER DIFFUSION TIME -75- ENHANCEMENT FACTOR _| 1_ 20 1 u 40 J- J 60 j u 80 EMITTER DIFFUSION TIME- te L 100 (minutes) FIGURE 24. PLOT OF ENHANCEMENT FACTOR vs. EMITTER DIFFUSION TIME -76- 120 BASE EMITTER BASE COLLECTOR ML COLLECTOR BASE 1 I b1 r I Ico\ t ^bo EMITTER \ A. AAAA FIGURE 25. EQUIVALENT CIRCUIT FOR A BIFURCATED TRANSISTOR -77- □ -INPUTS f\ -CALCULATED W VALUES C ] -EQUATIONS ■£16} -C203 -C27] 0 [22] (% V FIGURE 26. LOGICAL DEVELOPMENT OF THE GAIN CALCULATION -78- GAIN 600 - h fe =(Wo +W1 )/(-063W1 -.007W1 W0 ) 500 400 h 300 I 200 - W0 =.5 um 100 - J 1 .2 1 I I .4 LATERAL BASE WIDTH- W, «o I .6 I ; L .8 (microns) FIGURE 27. GAIN AS A FUNCTION OF LATERAL BASE WIDTH -79- .0 20 EMITTER SHEET RES.ot CATS 18 16 Re O r° A o f otun cm. of 14 Re=re +4.8 o oo/o 12 10 1 1 1 1 8 1 10 1 i i 12 IN-PROCESS EMITTER SHEET RESISTANCE r se (ohm—cm.) FIGURE 28. EMITTER SHEET RESISTANCE CATS vs. IN-PROCESS -80- i 14 BASE SHEET RESISTANCE at CATS 260 fc w W 240 © o /o 220 ohm on. © JT^ o°°o y 200 o sT * © ° ° ©°y^ oir 180 / ' cf ° yT © O y' 160 ■ 120 i Rb=rb+22 i i i i i i 140 160 180 200 IN-PROCESS BASE SHEET RESISTANCE ft, (ohm—cm.) FIGURE 29. BASE SHEET RESISTANCE CATS vs.lN-PROCESS -81- i 220 PINCH SHEET RESISTANCE at CATS 25 O I o 0 I 20 / / o of ° L o I0 RP i ° OO loo ohms/aq. / ° / 15 // ° 1 / o o °° ° ° o * o / 0 / /o / // ° / / Q / /o 10 y / 0 O / ° / ° X 5 1 ' ■ 5 10 15 IN-PROCESS PINCH SHEET RESISTANCE rp (ohms/square) FIGURE 30. PINCH SHEET RESISTANCE CATS vs.lN-PROCESS -82- 20 IN-PROCESS KELVIN CONTACT MEASUREMENT METALLIZED CATS MEASUREMENT FIGURE 31. PINCH SHEET RESISTANCE MEASUREMENTS -83- 50 GAIN TO PINCH RATIO \r— h/r vs. rp \ \ \ V 40 - \ \ ^ A \ \ \ \x ^h/r vs.RcA \ 30 - \\ h/r \ 20 \\ \\ \ \ 10 - \ \ i 0 1 .2 . 1 .4 1 1 .6 LATERAL BASE WIDTH- V^ _i.. 1 .8 (microns) FIGURE 32. GAIN TO PINCH RATIO vs.LATERAL BASE WIDTH -84- » 1.0 BREAKDOWN VOLTAGE per CHIN REFT 11 PUSH THROUGH 40 PLANAR JCN.BREAKDOWN 30 BV volts 20 - x-*^ <>*. MIN.TEST SPEC. 10 M1N.USEABLE BV * -BVc?o °-BVCbo _i I 100 ' 200 J 300 I I 400 GAIN- hfe FIGURE 33. BREAKDOWN VOLTAGE vs. GAIN -85- L. VITA Frederick J. Koons was born in Wilkes-Barre, Pennsylvania on September 3, 1933 to Fred and Loretta Koons. Vocational High School in June, 1951. April, 1953 to March, 1956. He graduated from Bethlehem He served in the U.S. Army from He did his undergraduate studies at the Pennsylvania State University and received a degree of Bachelor of Science in Physics from there 1n January, 1960. He joined AT4T Technol- ogies, formerly Western Electric, Allentown, 1n February, 1960 starting as a Development Engineer 1n the Diffused Silicon Transistor Engineering Department. At AT&T Technologies, Digital he is presently a , Senior Engineer in the Bipolar Integrated Circuit Device and Design Engineering Department. He is married to Ann Y. (nee McKeon) Koons and is the father of eight children, and has one grandchild. - 86