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Timestamp snooping: an approach for extending SMPs

Published: 12 November 2000 Publication History

Abstract

Symmetric muultiprocessor (SMP) servers provide superior performance for the commercial workloads that dominate the Internet. Our simulation results show that over one-third of cache misses by these applications result in cache-to-cache transfers, where the data is found in another processor's cache rather than in memory. SMPs are optimized for this case by using snooping protocols that broadcast address transactions to all processors. Conversely, directory-based shared-memory systems must indirectly locate the owner and sharers through a directory, resulting in larger average miss latencies.This paper proposes timestamp snooping, a technique that allows SMPs to i) utilize high-speed switched interconnection networks and ii) exploit physical locality by delivering address transactions to processors and memories without regard to order. Traditional snooping requires physical ordering of transactions. Timestamp snooping works by processing address transactions in a logical order. Logical time is maintained by adding a few bits per address transaction and having network switches perform a handshake to ensure on-time delivery. Processors and memories then reorder transactions based on their timestamps to establish a total order.We evaluate timestamp snooping with commercial workloads on a 16-processor SPARC system using the Simics full-system simulator. We simulate both an indirect (butterfly) and a direct (torus) network design. For OLTP, DSS, web serving, web searching, and one scientific application, timestamp snooping with the butterfly network runs 6-28% faster than directories, at a cost of 13-43% more link traffic. Similarly, with the torus network, timestamp snooping runs 6-29% faster for 17-37% more link traffic. Thus, timestamp snooping is worth considering when buying more interconnect bandwidth is easier than reducing interconnect latency.

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                              cover image ACM Conferences
                              ASPLOS IX: Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
                              November 2000
                              271 pages
                              ISBN:1581133170
                              DOI:10.1145/378993
                              • cover image ACM SIGOPS Operating Systems Review
                                ACM SIGOPS Operating Systems Review  Volume 34, Issue 5
                                Dec. 2000
                                269 pages
                                ISSN:0163-5980
                                DOI:10.1145/384264
                                Issue’s Table of Contents
                              • cover image ACM SIGARCH Computer Architecture News
                                ACM SIGARCH Computer Architecture News  Volume 28, Issue 5
                                Special Issue: Proceedings of the ninth international conference on Architectural support for programming languages and operating systems (ASPLOS '00)
                                Dec. 2000
                                269 pages
                                ISSN:0163-5964
                                DOI:10.1145/378995
                                Issue’s Table of Contents
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                              Published: 12 November 2000

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                              ASPLOS IX Paper Acceptance Rate 24 of 114 submissions, 21%;
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                              Cited By

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                              • (2022)Snooping Coherence ProtocolsA Primer on Memory Consistency and Cache Coherence10.1007/978-3-031-01764-3_7(107-149)Online publication date: 28-Mar-2022
                              • (2021)WiDir: A Wireless-Enabled Directory Cache Coherence Protocol2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00034(304-317)Online publication date: Feb-2021
                              • (2020)A Primer on Memory Consistency and Cache Coherence, Second EditionSynthesis Lectures on Computer Architecture10.2200/S00962ED2V01Y201910CAC04915:1(1-294)Online publication date: 4-Feb-2020
                              • (2018)ProtogenProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00030(247-260)Online publication date: 2-Jun-2018
                              • (2018)G-TSC: Timestamp Based Coherence for GPUs2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2018.00042(403-415)Online publication date: Feb-2018
                              • (2018)High-Performance GPU Transactional Memory via Eager Conflict Detection2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2018.00029(235-246)Online publication date: Feb-2018
                              • (2017)Efficient Sequential Consistency in GPUs via Relativistic Cache Coherence2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2017.40(625-636)Online publication date: Feb-2017
                              • (2017)PABST: Proportionally Allocated Bandwidth at the Source and Target2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2017.33(505-516)Online publication date: Feb-2017
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                              • (2016)Cache coherence: A walkthrough of mechanisms and challenges2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)10.1109/ICEEOT.2016.7755093(2251-2256)Online publication date: Mar-2016
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