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View all- Tsiskaridze NBarrett CTinelli C(2024)Generalized Optimization Modulo TheoriesAutomated Reasoning10.1007/978-3-031-63498-7_27(458-479)Online publication date: 1-Jul-2024
We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders ...
Abstract: We show that a 3-valued current mode CMOS 2-input BSC adder can be converted into a CMOS binary 4-2 counter or into a 1-digit Avizienis-like adder using a redundant number representation. Using a current mode algorithm to derive binary CMOS ...
This article presents the low-power ternary arithmetic logic unit (ALU) design in carbon nanotube field-effect transistor (CNFET) technology. CNFET unique characteristic of geometry-dependent threshold voltage is employed in the multi-valued logic ...
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