Nothing Special   »   [go: up one dir, main page]

skip to main content
10.1145/3542954.3543065acmotherconferencesArticle/Chapter ViewAbstractPublication PagesiccaConference Proceedingsconference-collections
research-article

Receiving & Processing of High-Speed Data in Digital Storage Oscilloscope (DSO)

Published: 11 August 2022 Publication History

Abstract

Signal acquisition and processing technology is a key component of information technology, and the use of data acquisition methods is very useful in the analysis and measurement process. But the difficult challenge is to acquire the signals correctly and process them correctly without losing any information. As a standard signal measurement tool, in the manufacture, testing, and support of electronic systems, a digital storage oscilloscope (DSO) is essential. A field-programmable gate array (FPGA) is a general-purpose chip frequently used in data acquisition systems for receiving sample data from analog-to-digital converters (A / D). However, due to limitations in manufacturing technology, FPGAs cannot directly handle high-speed acquisitions. Need to change high-speed data to low-speed data to meet the processing speed of FPGA. If one can't receive the data accurately, it is possible to get wrong information, and the processing part is another important part of data acquisition. To observe the details of the signal, the sampling rate conversion process needs to be performed. Analyze the A / D's high-speed data acquisition capability and the FPGA's high-performance data processing capacity, and configured deserialization module ISERDES which can help to reduce data rate from the ADC. The main method here is Interpolation and decimation where 5, 10 times interpolation and 100-time decimation are accomplished. According to the signals of different frequencies, through the combination of interpolation and decimation, the multi-rate sampling rate conversion can be realized and achieved into the DSO.

References

[1]
Y. Zhang,C. Yi,and J. Wang. Asynchronous FIFO Implementation Using FPGA .2011, (Iceoe):207–209. https://doi.org/10.1109/ICEOE.2011.6013339
[2]
Jun J, Peng Y. A study on improving the abnormal signal detection ability of digital storage oscilloscope. In 2013 IEEE 11th International Conference on Dependable, Autonomic and Secure Computing 2013 Dec 21 (pp. 244-247). https://doi.org/10.1109/DASC.2013.70
[3]
Sekiguchi M, Nakaya H, Kataza H, Miyazaki S. High-speed data acquisition system messia for subaru. In Optical Detectors for Astronomy 1998 (pp. 157-164). https://doi.org/10.1007/978-94-011-5262-4_26
[4]
Bulgakov AY, V'yukhin VN, Popov YA. A 24-bit data acquisition system. Instruments and Experimental Techniques [J]. 2001 Mar 1;44(2):180-2. https://doi.org/10.1023/A:1017554717595
[5]
PEREIRA J M D, “The history and technology of oscilloscopes”, IEEE Trans. Instrumentation & Measurement, vol. 9, no. 6, pp. 27-35, 2006R. Nicole, “Title of paper with only first word capitalized,” J. Name Stand. Abbrev., in press. https://doi.org/10.1109/MIM.2006.250640
[6]
JOHNNIE H, “An oscilloscope's 3rd dimension-trans”. Global Electronics China, no. 5, pp. 72-75, 2006M. Young, The Technical Writer's Handbook. Mill Valley, CA: University Science, 1989.
[7]
Zeng H, Xiang C, Ye P, Wang H. Research on a method to improve the waveform acquire rate of DSO. In 2009 9th International Conference on Electronic Measurement & Instruments 2009 Aug 16 (pp. 1-974). https://doi.org/10.1109/ICEMI.2009.5274469
[8]
Xie M, Zhao FH, Tang GP. A Realization of Large Capacity, High-speed Data Acquisition and Storage System. In Applied Mechanics and Materials 2014, Vol. 568, pp. 162-167. https://doi.org/10.4028/www.scientific.net/AMM.568-570.162
[9]
Wang Liying. High-resolution oscilloscope to meet the measurement of small signals. Electronics, 2013: 08: 15-24
[10]
Crochiere RE, Rabiner LR. Interpolation and decimation of digital signals—A tutorial review. Proceedings of the IEEE. 1981 Mar;69(3):300-31. https://doi.org/10.1109/PROC.1981.11969
[11]
A. V. Oppenheim, R. W. Schafer and J. R. Buck, “Discrete-time signaprocessing. 1999
[12]
Proakis JG. Digital signal processing: principles algorithms and applications. Pearson Education India. 2001
[13]
Eminaga Y, Coskun A, Moschos SA, Kale I. Low complexity all-pass based polyphase decimation filters for ECG monitoring. In 2015 11th Conference on Ph. D. Research in Microelectronics and Electronics (PRIME), 2015 Jun 29, (pp. 322-325). https://doi.org/10.1109/PRIME.2015.7251400
[14]
Richard G. Lyons. Understand digital signal processing,Third edition. 2010, November 2010
[15]
P. Fiala and R. Linhart, "High performance polyphase FIR filter structures in VHDL language for Software Defined Radio based on FPGA. 2014 International Conference on Applied Electronics, Pilsen, 2014, pp. 83-86. https://doi.org/10.1109/AE.2014.7011674
[16]
Yu Z, Peng Y, Haoyu Y, Jie M, Kuojun Y. An efficient structure of multi-rate interpolation in digital storage oscilloscope. In 2019 14th IEEE International Conference on Electronic Measurement & Instruments (ICEMI) 2019 Nov 1 (pp. 344-350). IEEE. https://doi.org/10.1109/ICEMI46757.2019.9101895
[17]
Kuojun Y, Yu Z, Zhixiang P, Jiali S, Peng Y. A novel decimation method in parallel based acquisition system. In 2019 14th IEEE International Conference on Electronic Measurement & Instruments (ICEMI) 2019 Nov 1 (pp. 1855-1860). IEEE. https://doi.org/10.1109/ICEMI46757.2019.9101672

Cited By

View all

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Other conferences
ICCA '22: Proceedings of the 2nd International Conference on Computing Advancements
March 2022
543 pages
ISBN:9781450397346
DOI:10.1145/3542954
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 August 2022

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. ADC
  2. Decimation
  3. FPGA
  4. ISERDES
  5. Interpolation
  6. Parallel processing
  7. Storage System

Qualifiers

  • Research-article
  • Research
  • Refereed limited

Conference

ICCA 2022

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • 0
    Total Citations
  • 40
    Total Downloads
  • Downloads (Last 12 months)15
  • Downloads (Last 6 weeks)1
Reflects downloads up to 27 Nov 2024

Other Metrics

Citations

Cited By

View all

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

HTML Format

View this article in HTML Format.

HTML Format

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media